TM4C129ENCZAD Datasheet, PDF (239/2037 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129ENCZAD Microcontroller
5.2.5.2
Clock Configuration
The Run and Sleep Mode Configuration Register (RSCLKCFG) provides control for the system
clock in run and sleep mode. The Deep Sleep Clock Configuration register (DSCLKCFG) specifies
the behavior of the clock system while in deep sleep mode. These registers control the following
clock functionality:
■ Source of system clock in run and sleep mode
■ Source of system clock in deep-sleep mode
■ Enabling/disabling of PLL-derived system clock
■ Clock divisors for PLL or oscillator, depending on what is enabled
■ Enabling of memory timing parameters for flash
Providing further configuration, the PLL Frequency n (PLLFREQn) registers allow the PLL VCO
frequency (f_VCO) to multiplied or divided by programmable values depending on the system clock
speed required.
Table 5-4 on page 239 shows the state of the clock sources following a Power-On Reset.
Table 5-4. Clock Source State Following POR
Clock Source
PLL
MOSC
LFIOSC
PIOSC
HIB RTCOSC
Disabled/Powered Off
Disabled/Powered Off
Enabled
Enabled
Disabled
Power-On Reset State
Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system
clock signal and can be individually enabled/disabled.
Note: The clock sources in Figure 5-5 include a superset of peripherals available in the family.
Some peripheral clock sources may not be present on your specific device.
June 18, 2014
239
Texas Instruments-Production Data