MSP430G2333-Q1 Datasheet, PDF (8/62 Pages) Texas Instruments – Automotive Mixed-Signal Microcontroller

MSP430G2333-Q1
SLAS802A – OCTOBER 2013 – REVISED MARCH 2014
8 Detailed Description
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8.1 CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
8.2 Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
Instruction Set (continued)
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
INSTRUCTION FORMAT
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
Table 3. Instruction Word Formats
EXAMPLE
ADD R4,R5
CALL R8
JNE
OPERATION
R4 + R5 ---> R5
PC -->(TOS), R8--> PC
Jump-on-equal bit = 0
ADDRESS MODE
Register
Indexed
Symbolic (PC relative)
Absolute
Indirect
Table 4. Address Mode Descriptions⁽¹⁾
SD
✓✓
✓✓
✓✓
✓✓
✓
SYNTAX
MOV Rs,Rd
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM,&TCDAT
MOV @Rn,Y(Rm)
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
MOV @R10,Tab(R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
Immediate
✓
MOV #X,TONI
MOV #45,TONI
(1) S = source, D = destination
OPERATION
R10 -- --> R11
M(2+R5) -- --> M(6+R6)
M(EDE) -- --> M(TONI)
M(MEM) -- --> M(TCDAT)
M(R10) -- --> M(Tab+R6)
M(R10) -- --> R11
R10 + 2-- --> R10
#45 -- --> M(TONI)
8
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