LMK00308 Datasheet, PDF (8/25 Pages) Texas Instruments – 3-GHz 8-Output Differential Clock Buffer/Level Translator

Symbol
f_{CLKout_FS}
f_{CLKout_RS}
Jitter_ADD
Noise Floor
DUTY
V_OD
ΔV_OD
V_OS
ΔV_OS
I_SA
I_SB
I_SAB
t_R
t_F
Parameter
Conditions
Min
LVDS Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
Maximum Output Frequency
Full V_OD Swing
(Note 20, Note 21)
V_OD ≥ 250 mV,
R_L = 100 Ω differential
1.0
Maximum Output Frequency
Reduced V_OD Swing
(Note 20, Note 21)
V_OD ≥ 200 mV,
R_L = 100 Ω differential
1.5
CLKin: 100 MHz, Slew
Additive RMS Jitter
Integration Bandwidth
1 MHz to 20 MHz
(Note 16)
Vcco = 3.3 V,
R_L = 100 Ω
differential
rate ≥ 3 V/ns
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns
CLKin: 625 MHz, Slew
rate ≥ 3 V/ns
CLKin: 100 MHz, Slew
Noise Floor
f_OFFSET ≥ 10 MHz
Vcco = 3.3 V,
R_L = 100 Ω
differential
rate ≥ 3 V/ns
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns
CLKin: 625 MHz, Slew
rate ≥ 3 V/ns
Duty Cycle (Note 20)
50% input clock duty cycle
45
Output Voltage Swing
(Note 14)
250
Change in Magnitude of V_OD for
T_A = 25 °C,
-50
Complementary Output States
DC Measurement,
Output Offset Voltage
Change in Magnitude of V_OS for
Complementary Output States
R_L = 100 Ω differential
1.125
-35
Output Short Circuit Current
T_A = 25 °C,
-24
Single Ended
Single ended outputs shorted to GND
Output Short Circuit Current
Differential
Complementary outputs tied together
-12
Output Rise Time
20% to 80%
Output Fall Time
80% to 20%
R_L = 100 Ω differential
Typ Max
1.6
2.1
89
77
37
-159.5
-157.0
-152.7
55
400 450
50
1.25 1.375
35
24
12
175
175
Units
GHz
GHz
fs
dBc/Hz
%
mV
mV
V
mV
mA
mA
ps
ps
www.ti.com
8