LMK00308 Datasheet, PDF (22/25 Pages) Texas Instruments – 3-GHz 8-Output Differential Clock Buffer/Level Translator

14.4.2 Power Supply Bypassing
The Vcc and Vcco power supplies should have a high-fre-
quency bypass capacitor, such as 0.1 uF or 0.01 uF, placed
very close to each supply pin. 1 uF to 10 uF decoupling ca-
pacitors should also be placed nearby the device between the
supply and ground planes. All bypass and decoupling capac-
itors should have short connections to the supply and ground
plane through a short trace or via to minimize series induc-
tance.
14.4.2.1 Power Supply Ripple Rejection
In practical system applications, power supply noise (ripple)
can be generated from switching power supplies, digital
ASICs or FPGAs, etc. While power supply bypassing will help
filter out some of this noise, it is important to understand the
effect of power supply ripple on the device performance.
When a single-tone sinusoidal signal is applied to the power
supply of a clock distribution device, such as LMK00308, it
can produce narrow-band phase modulation as well as am-
plitude modulation on the clock output (carrier). In the single-
side band phase noise spectrum, the ripple-induced phase
modulation appears as a phase spur level relative to the car-
rier (measured in dBc).
For the LMK00308, power supply ripple rejection, or PSRR,
was measured as the single-sideband phase spur level (in
dBc) modulated onto the clock output when a ripple signal
was injected onto the Vcco supply. The PSRR test setup is
shown in Figure 16.
phase spur levels for the differential output types at 156.25
MHz and 312.5 MHz . The LMK00308 exhibits very good and
well-behaved PSRR characteristics across the ripple frequen-
cy range for all differential output types. The phase spur levels
for LVPECL are below -64 dBc at 156.25 MHz and below -62
dBc at 312.5 MHz. Using Equation 12, these phase spur lev-
els translate to Deterministic Jitter values of 2.57 ps pk-pk at
156.25 MHz and 1.62 ps pk-pk at 312.5 MHz. Testing has
shown that the PSRR performance of the device improves for
Vcco = 3.3 V under the same ripple amplitude and frequency
conditions.
14.4.3 Thermal Management
Power dissipation in the LMK00308 device can be high
enough to require attention to thermal management. For re-
liability and performance reasons the die temperature should
be limited to a maximum of 125 °C. That is, as an estimate,
T_A (ambient temperature) plus device power dissipation times
θ_JA should not exceed 125 °C.
The package of the device has an exposed pad that provides
the primary heat removal path as well as excellent electrical
grounding to the printed circuit board. To maximize the re-
moval of heat from the package a thermal land pattern in-
cluding multiple vias to a ground plane must be incorporated
on the PCB within the footprint of the package. The exposed
pad must be soldered down to ensure adequate heat con-
duction out of the package.
A recommended land and via pattern is shown in Figure 17.
More information on soldering LLP packages can be obtained
at: http://www.national.com/analog/packaging/.
A recommended footprint including recommended solder
mask and solder paste layers can be found at: http://
www.national.com/analog/packaging/gerber for the SQA40A
package.
FIGURE 16. PSRR Test Setup
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A signal generator was used to inject a sinusoidal signal onto
the Vcco supply of the DUT board, and the peak-to-peak rip-
ple amplitude was measured at the Vcco pins of the device.
A limiting amplifier was used to remove amplitude modulation
on the differential output clock and convert it to a single-ended
signal for the phase noise analyzer. The phase spur level
measurements were taken for clock frequencies of 156.25
MHz and 312.5 MHz under the following power supply ripple
conditions:
• Ripple amplitude: 100 mVpp on Vcco = 2.5 V
• Ripple frequencies: 100 kHz, 1 MHz, and 10 MHz
Assuming no amplitude modulation effects and small index
modulation, the peak-to-peak deterministic jitter (DJ) can be
calculated using the measured single-sideband phase spur
level (PSRR) as follows:
DJ (ps pk-pk) = [(2*10^{(PSRR / 20)}) / (π*f_CLK)] * 10¹² (12)
The “PSRR vs. Ripple Frequency” plots in Section 13.0 Typ-
ical Performance Characteristics show the ripple-induced
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FIGURE 17. Recommended Land and Via Pattern
To minimize junction temperature it is recommended that a
simple heat sink be built into the PCB (if the ground plane
layer is not exposed). This is done by including a copper area
of about 2 square inches on the opposite side of the PCB from
the device. This copper area may be plated or solder coated
to prevent corrosion but should not have conformal coating (if
possible), which could provide thermal insulation. The vias
shown in Figure 17 should connect these top and bottom
copper layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side
of the board to where it can be more effectively dissipated.
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