LMK00308 Datasheet, PDF (4/25 Pages) Texas Instruments – 3-GHz 8-Output Differential Clock Buffer/Level Translator

7.0 Functional Description
The LMK00308 is an 8-output differential clock fanout buffer
with low additive jitter that can operate up to 3.1 GHz. It fea-
tures a 3:1 input multiplexer with an optional crystal oscillator
input, two banks of 4 differential outputs with multi-mode
buffers (LVPECL, LVDS, HCSL, or Hi-Z), one LVCMOS out-
put, and 3 independent output buffer supplies. The input
selection and output buffer modes are controlled via pin strap-
ping. The device is offered in a 40-pin LLP package and
leverages much of the high-speed, low-noise circuit design
employed in the LMK04800 family of clock conditioners.
7.1 V_CC and V_CCO Power Supplies
The LMK00308 has a 3.3 V core power supply (V_CC) and 3
independent 3.3 V/2.5 V output power supplies (V_CCOA,
V_CCOB, V_CCOC). Output supply operation at 2.5 V enables low-
er power consumption and output-level compatibility with 2.5
V receiver devices. The output levels for LVPECL (V_OH, V_OL)
and LVCMOS (V_OH) are referenced to the respective Vcco
supply, while the output levels for LVDS and HCSL are rela-
tively constant over the specified Vcco range. Refer to Sec-
tion 14.4 Power Supply and Thermal Considerations for
additional supply related considerations, such as power dis-
sipation, power supply bypassing, and power supply ripple
rejection (PSRR).
Note 4: Care should be taken to ensure the Vcco voltages do not exceed
the Vcc voltage to prevent turning-on the internal ESD protection circuitry.
7.2 Clock Inputs
The input clock can be selected from CLKin0/CLKin0*,
CLKin1/CLKin1*, or OSCin. Clock input selection is controlled
using the CLKin_SEL[1:0] inputs as shown in Table 1. Refer
to Section 14.1 Driving the Clock Inputs for clock input re-
quirements. When CLKin0 or CLKin1 is selected, the crystal
circuit is powered down. When OSCin is selected, the crystal
oscillator circuit will start-up and its clock will be distributed to
all outputs. Refer to Section 14.2 Crystal Interface for more
information. Alternatively, OSCin may be be driven by a sin-
gle-ended clock (up to 250 MHz) instead of a crystal.
TABLE 1. Input Selection
CLKin_SEL1 CLKin_SEL0
Selected Input
0
0
CLKin0, CLKin0*
0
1
CLKin1, CLKin1*
1
X
OSCin
Table 2 shows the output logic state vs. input state when ei-
ther CLKin0/CLKin0* or CLKin1/CLKin1* is selected. When
OSCin is selected, the output state will be an inverted copy of
the OSCin input state.
TABLE 2. CLKin Input vs. Output States
State of
Selected CLKin
State of
Enabled Outputs
CLKinX and CLKinX*
inputs floating
Logic low
CLKinX and CLKinX*
inputs shorted together
Logic low
CLKin logic low
Logic low
CLKin logic high
Logic high
7.3 Clock Outputs
The differential output buffer type for Bank A and Bank B out-
puts can be separately configured using the CLKoutA_TYPE
[1:0] and CLKoutB_TYPE[1:0] inputs, respectively, as shown
in Table 3. For applications where all differential outputs are
not needed, any unused output pin should be left floating with
a minimum copper length (Note 5) to minimize capacitance
and potential coupling and reduce power consumption. If an
entire output bank will not be used, it is recommended to dis-
able/Hi-Z the bank to reduce power. Refer to Section 14.3
Termination and Use of Clock Drivers for more information on
output interface and termination techniques.
Note 5: For best soldering practices, the minimum trace length for any
unused output pin should extend to include the pin solder mask. This way
during reflow, the solder has the same copper area as connected pins. This
allows for good, uniform fillet solder joints helping to keep the IC level during
reflow.
TABLE 3. Differential Output Buffer Type Selection
CLKoutX_ CLKoutX_
TYPE1
TYPE0
CLKoutX Buffer Type
(Bank A or B)
0
0
LVPECL
0
1
LVDS
1
0
HCSL
1
1
Disabled (Hi-Z)
7.3.1 Reference Output
The reference output (REFout) provides a LVCMOS copy of
the selected input clock. The LVCMOS output high level is
referenced to the Vcco voltage. REFout can be enabled or
disabled using the enable input pin, REFout_EN, as shown in
Table 4.
TABLE 4. Reference Output Enable
REFout_EN
REFout State
0
Disabled (Hi-Z)
1
Enabled
The REFout_EN input is internally synchronized with the se-
lected input clock by the SYNC block. This synchronizing
function prevents glitches and runt pulses from occurring on
the REFout clock when enabled or disabled. REFout will be
enabled within 3 cycles (t_EN) of the input clock after
REFout_EN is toggled high. REFout will be disabled within 3
cycles (t_DIS) of the input clock after REFout_EN is toggled low.
When REFout is disabled, the use of a resistive loading can
be used to set the output to a predetermined level. For ex-
ample, if REFout is configured with a 1 kΩ load to ground,
then the output will be pulled to low when disabled.
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