LMK00308 Datasheet, PDF (5/25 Pages) Texas Instruments – 3-GHz 8-Output Differential Clock Buffer/Level Translator

8.0 Absolute Maximum Ratings (Note 6, Note 7)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for
availability and specifications.
Parameter
Supply Voltages
Input Voltage
Storage Temperature Range
Lead Temperature (solder 4 s)
Junction Temperature
Symbol
V_CC, V_CCO
V_IN
T_STG
T_L
T_J
Ratings
-0.3 to 3.6
-0.3 to (V_CC + 0.3)
-65 to +150
+260
+150
Units
V
V
°C
°C
°C
9.0 Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Ambient Temperature Range
Junction Temperature
Core Supply Voltage Range
Output Supply Voltage Range (Note 8,
Note 9)
T_A
T_J
V_CC
V_CCO
-40
25
85
°C
125
°C
3.15
3.3
3.45
V
3.3 – 5%
2.5 – 5%
3.3
2.5
3.3 + 5%
2.5 + 5%
V
Note 6: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see Section 11.0 Electrical
Characteristics. The guaranteed specifications apply only to the test conditions listed.
Note 7: This device is a high-performance integrated circuit with an ESD rating up to 2 kV Human Body Model, up to 150 V Machine Model, and up to 750 V
Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations.
Note 8: The output supply voltages/pins (V_CCOA, V_CCOB, and V_CCOC) will be referred to generally as V_CCO when no distinction is needed, or when the output supply
can be inferred by the output bank/type.
Note 9: Vcco should be less than or equal to Vcc (Vcco ≤ Vcc).
10.0 Package Thermal Resistance
Package
40-Lead LLP (Note 10)
θ_JA
31.4 °C/W
θ_{JC (DAP)}
7.2 °C/W
Note 10: Specification assumes 9 thermal vias connect the die attach pad (DAP) to the embedded copper plane on the 4-layer JEDEC board. These vias play a
key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.
11.0 Electrical Characteristics Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ±
5%, -40 °C ≤ T_A ≤ 85 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric
norms at Vcc = 3.3 V, Vcco = 3.3 V, T_A = 25 °C, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed. (Note 8, Note 11)
Symbol
Parameter
I_{CC_CORE}
I_{CC_PECL}
I_{CC_LVDS}
I_{CC_HCSL}
I_{CC_CMOS}
Core Supply Current, All Outputs
Disabled
Additive Core Supply Current,
Per LVPECL Bank Enabled
Additive Core Supply Current,
Per LVDS Bank Enabled
Additive Core Supply Current,
Per HCSL Bank Enabled
Additive Core Supply Current,
LVCMOS Output Enabled
I_{CCO_PECL}
Additive Output Supply Current,
Per LVPECL Bank Enabled
Conditions
Current Consumption
CLKinX selected
OSCin selected
Includes Output Bank Bias and Load
Currents, R_T = 50 Ω to Vcco - 2V
on all outputs in bank
Min Typ Max Units
8.5 10.5
mA
10
13.5
mA
20
26.5
mA
25
30.5
mA
31
38.5
mA
3.5
5.5
mA
132 160
mA
5
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