LMK00308 Datasheet, PDF (16/25 Pages) Texas Instruments – 3-GHz 8-Output Differential Clock Buffer/Level Translator

14.0 Application Information
14.1 Driving the Clock Inputs
The LMK00308 has two universal inputs (CLKin0/CLKin0*
and CLKin1/CLKin1*) that can accept AC- or DC-coupled
3.3V/2.5V LVPECL, LVDS, CML, SSTL, and other differential
and single-ended signals that meet the input requirements
specified in the Section 11.0 Electrical Characteristics. The
device can accept a wide range of signals due to its wide input
common mode voltage range (V_CM ) and input voltage swing
(V_ID) / dynamic range. For 50% duty cycle and DC-balanced
signals, AC coupling may also be employed to shift the input
signal to within the V_CM range. Refer to Section 14.3 Termi-
nation and Use of Clock Drivers for signal interfacing and
termination techniques.
To achieve the best possible phase noise and jitter perfor-
mance, it is mandatory for the input to have high slew rate of
3 V/ns (differential) or higher. Driving the input with a lower
slew rate will degrade the noise floor and jitter. For this rea-
son, a differential signal input is recommended over single-
ended because it typically provides higher slew rate and
common-mode-rejection. Refer to the “Noise Floor vs. CLKin
Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in
Section 13.0 Typical Performance Characteristics.
While it is recommended to drive the CLKin0 and CLKin1 with
a differential signal input, it is possible to drive them with a
single-ended clock. Again, the single-ended input slew rate
should be as high as possible to minimize performance degra-
dation. The CLKin input has an internal bias voltage of about
1.4 V, so the input can be AC coupled as shown in Figure 3.
30177629
FIGURE 4. Single-Ended LVCMOS Input, DC Coupling
with Common Mode Biasing
If the crystal oscillator circuit is not used, it is possible to drive
the OSCin input with an single-ended external clock as shown
in Figure 5. The input clock should be AC coupled to the OS-
Cin pin, which has an internally-generated input bias voltage,
and the OSCout pin should be left floating. While OSCin pro-
vides an alternative input to multiplex an external clock, it is
recommended to use either differential input (CLKinX) since
it offers higher operating frequency, better common mode and
power supply noise rejection, and greater performance over
supply voltage and temperature variations.
30177628
FIGURE 3. Single-Ended LVCMOS Input, AC Coupling
A single-ended clock may also be DC coupled to CLKinX as
shown in Figure 4. If the DC coupled input swing has a com-
mon mode level near the device's internal bias voltage of 1.4
V, then only a 0.1 uF bypass cap is required on CLKinX*.
Otherwise, if the input swing is not optimally centered near
the internal bias voltage, then CLKinX* should be externally
biased to the midpoint voltage of the input swing. This can be
achieved using external biasing resistors, R_B1 and R_B2, or an-
other low-noise voltage reference. The external bias voltage
should be within the specified input common voltage (V_CM)
range. This will ensure the input swing crosses the threshold
voltage at a point where the input slew rate is the highest.
30177630
FIGURE 5. Driving OSCin with a Single-Ended Input
14.2 Crystal Interface
The LMK00308 has an integrated crystal oscillator circuit that
supports a fundamental mode, AT-cut crystal. The crystal in-
terface is shown in Figure 6.
30177609
FIGURE 6. Crystal Interface
The load capacitance (C_L) is specific to the crystal, but usually
on the order of 18 - 20 pF. While C_L is specified for the crystal,
the OSCin input capacitance (C_IN = 1 pF typical) of the device
and PCB stray capacitance (C_STRAY ~ 1~3 pF) can affect the
discrete load capacitor values, C₁ and C₂.
For the parallel resonant circuit, the discrete capacitor values
can be calculated as follows:
C_L = (C₁ * C₂) / (C₁ + C₂) + C_IN + C_STRAY
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