LMK00308 Datasheet, PDF (17/25 Pages) Texas Instruments – 3-GHz 8-Output Differential Clock Buffer/Level Translator

Typically, C₁ = C₂ for optimum symmetry, so Equation 1 can
be rewritten in terms of C₁ only:
C_L = C₁₂ / (2 * C₁) + C_IN + C_STRAY
(2)
Finally, solve for C₁:
C₁ = (C_L - C_IN - C_STRAY)*2
(3)
Section 11.0 Electrical Characteristics provides crystal inter-
face specifications with conditions that ensure start-up of the
crystal, but it does not specify crystal power dissipation. The
designer will need to ensure the crystal power dissipation
does not exceed the maximum drive level specified by the
crystal manufacturer. Overdriving the crystal can cause pre-
mature aging, frequency shift, and eventual failure. Drive level
should be held at a sufficient level necessary to start-up and
maintain steady-state operation.
The power dissipated in the crystal, P_XTAL, can be computed
by:
P_XTAL = I_RMS2 * R_ESR*(1 + C₀/C_L)²
(4)
Where:
• I_RMS is the RMS current through the crystal.
• R_ESR is the max. equivalent series resistance specified for
the crystal
• C_L is the load capacitance specified for the crystal
• C₀ is the min. shunt capacitance specified for the crystal
I_RMS can be measured using a current probe (e.g. Tektronix
CT-6 or equivalent) placed on the leg of the crystal connected
to OSCout with the oscillation circuit active.
As shown in Figure 6, an external resistor, R_LIM, can be used
to limit the crystal drive level, if necessary. If the power dissi-
pated in the selected crystal is higher than the drive level
specified for the crystal with R_LIM shorted, then a larger resis-
tor value is mandatory to avoid overdriving the crystal. How-
ever, if the power dissipated in the crystal is less than the drive
level with R_LIM shorted, then a zero value for R_LIM can be used.
As a starting point, a suggested value for R_LIM is 1.5 kΩ.
14.3 Termination and Use of Clock Drivers
When terminating clock drivers keep in mind these guidelines
for optimum phase noise and jitter performance:
• Transmission line theory should be followed for good
impedance matching to prevent reflections.
• Clock drivers should be presented with the proper loads.
— LVDS outputs are current drivers and require a closed
current loop.
— HCSL drivers are switched current outputs and require
a DC path to ground via 50 Ω termination.
— LVPECL outputs are open emitter and require a DC
path to ground.
• Receivers should be presented with a signal biased to
their specified DC bias level (common mode voltage) for
proper operation. Some receivers have self-biasing inputs
that automatically bias to the proper voltage level; in this
case, the signal should normally be AC coupled.
It is possible to drive a non-LVPECL or non-LVDS receiver
with a LVDS or LVPECL driver as long as the above guide-
lines are followed. Check the datasheet of the receiver or
input being driven to determine the best termination and cou-
pling method to be sure the receiver is biased at the optimum
DC voltage (common mode voltage).
14.3.1 Termination for DC Coupled Differential Operation
For DC coupled operation of an LVDS driver, terminate with
100 Ω as close as possible to the LVDS receiver as shown in
Figure 7.
30177620
FIGURE 7. Differential LVDS Operation, DC Coupling,
No Biasing by the Receiver
For DC coupled operation of an HCSL driver, terminate with
50 Ω to ground near the driver output as shown in Figure 8.
Series resistors, Rs, may be used to limit overshoot due to
the fast transient current. Because HCSL drivers require a DC
path to ground, AC coupling is not allowed between the output
drivers and the 50 Ω termination resistors.
30177690
FIGURE 8. HCSL Operation, DC Coupling
For DC coupled operation of an LVPECL driver, terminate
with 50 Ω to Vcco - 2 V as shown in Figure 9. Alternatively
terminate with a Thevenin equivalent circuit as shown in Fig-
ure 10 for Vcco (output driver supply voltage) = 3.3 V and 2.5
V. In the Thevenin equivalent circuit, the resistor dividers set
the output termination voltage (V_TT) to Vcco - 2 V.
30177621
FIGURE 9. Differential LVPECL Operation, DC Coupling
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