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DS92LV1224_15 Datasheet, PDF (8/23 Pages) Texas Instruments – 30-66 MHz 10 Bit Bus LVDS Deserializer
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DS92LV1224
SNLS189A – APRIL 2005 – REVISED APRIL 2013
Deserializer Switching Characteristics(1)(2)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbo
l
Parameter
Conditions Pin/Freq.
Min
Typ
tRCP
Receiver out Clock
Period
tRCP = tTCP
RCLK
15.15
tCLH
CMOS/TTL Low-to-High
Transition Time
CL = 15 pF
Rout(0-9),
LOCK,
RCLK
1.2
See Figure 3
tCHL
CMOS/TTL High-to-Low
Transition Time
1.1
All Temp./ All
Freq.
1.75*tRCP+1.25
1.75*tRCP+3.75
tDD
Deserializer Delay
See Figure 5
Room Temp./
3.3V/30MHz
Room Temp./
3.3V/40MHz
1.75*tRCP+2.25
1.75*tRCP+2.25
1.75*tRCP+3.75
1.75*tRCP+3.75
Room Temp./
3.3V/66MHz
1.75*tRCP+2.75
1.75*tRCP+3.75
RCLK
30MHz
0.4*tRCP
0.5*tRCP
tROS
ROUT Data Valid before
RCLK
See Figure 6
RCLK
40MHz
0.4*tRCP
0.5*tRCP
RCLK
66MHz
0.38*tRCP
0.5*tRCP
tROH
ROUT Data valid after
RCLK
See Figure 6
tRDC
tHZR
tLZR
tZHR
tZLR
tDSR1
RCLK Duty Cycle
HIGH to TRI-STATE Delay
LOW to TRI-STATE Delay
See Figure 7
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer PLL Lock time
from PWRDWN (with
SYNCPAT)
30MHz
40MHz
66MHz
Rout(0-9)
30MHz
40MHz
66MHz
−0.4*tRCP
−0.4*tRCP
−0.38*tRCP
45
−0.5*tRCP
−0.5*tRCP
−0.5*tRCP
50
2.8
2.8
4.2
4.2
1.68
1.31
0.84
30MHz
0.62
tDSR2
Deserializer PLL Lock time
from SYNCPAT
40MHz
0.47
66MHz
0.29
tZHLK
TRI-STATE to HIGH Delay
(power-up)
LOCK
3.7
30 MHz
650
950
tRNM
Deserializer Noise Margin See (3)
40 MHz
450
730
66 MHz
250
400
www.ti.com
Max
33.33
Units
ns
4
ns
4
ns
1.75*tRCP+6.25
ns
1.75*tRCP+5.25
ns
1.75*tRCP+5.25
ns
1.75*tRCP+4.75
ns
ns
ns
ns
ns
ns
ns
55
%
10
ns
10
ns
10
ns
10
ns
3
μs
3
μs
3
μs
1
μs
1
μs
0.8
μs
12
ns
ps
ps
ps
(1) tLLHT and tLHLT specifications are Guranteed By Design (GBD) using statistical analysis.
(2) Because the Serializer is in TRI-STATE mode, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
(3) tRNM is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. The
Deserializer Noise Margin is Guaranteed By Design (GBD) using statistical analysis.
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