DS92LV1224_15 Datasheet, PDF (2/23 Pages) Texas Instruments – 30-66 MHz 10 Bit Bus LVDS Deserializer

DS92LV1224
SNLS189A – APRIL 2005 – REVISED APRIL 2013
www.ti.com
Functional Description
The DS92LV1224 is a 10-bit Deserializer device which together with a compatible serializer (i.e. DS92LV1023E)
forms a chipset designed to transmit data over FR-4 printed circuit board backplanes and balanced copper
cables at clock speeds from 30 MHz to 66 MHz.
The chipset has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two
passive states: Powerdown and TRI-STATE.
The following sections describe each operation and passive state.
Initialization
Initialization of both devices must occur before data transmission begins. Initialization refers to synchronization of
the Serializer and Deserializer PLL's to local clocks, which may be the same or separate. Afterwards,
synchronization of the Deserializer to Serializer occurs.
Step 1: When you apply V_CC to both Serializer and/or Deserializer, the respective outputs enter TRI-STATE, and
on-chip power-on circuitry disables internal circuitry. When V_CC reaches V_CCOK (2.5V) the PLL in each device
begins locking to a local clock. For the Serializer, the local clock is the transmit clock (TCLK) provided by the
source ASIC or other device. For the Deserializer, you must apply a local clock to the REFCLK pin.
The Serializer outputs remain in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the
Serializer is now ready to send data or SYNC patterns, depending on the levels of the SYNC1 and SYNC2 inputs
or a data stream. The SYNC pattern sent by the Serializer consists of six ones and six zeros switching at the
input clock rate.
Note that the Deserializer LOCK output will remain high while its PLL locks to the incoming data or to SYNC
patterns on the input.
Step 2: The Deserializer PLL must synchronize to the Serializer to complete initialization. The Deserializer will
lock to non-repetitive data patterns. However, the transmission of SYNC patterns enables the Deserializer to lock
to the Serializer signal within a specified time.
The user's application determines control of the SYNC1 and SYNC 2 pins. One recommendation is a direct
feedback loop from the LOCK pin. Under all circumstances, the Serializer stops sending SYNC patterns after
both SYNC inputs return low.
When the Deserializer detects edge transitions at the Bus LVDS input, it will attempt to lock to the embedded
clock information. When the Deserializer locks to the Bus LVDS clock, the LOCK output will go low. When LOCK
is low, the Deserializer outputs represent incoming Bus LVDS data.
Data Transfer
After initialization, the Serializer will accept data from inputs DIN0–DIN9. The Serializer uses the TCLK input to
latch incoming Data. The TCLK_R/F pin selects which edge the Serializer uses to strobe incoming data.
TCLK_R/F high selects the rising edge for clocking data and low selects the falling edge. If either of the SYNC
inputs is high for 5*TCLK cycles, the data at DIN0-DIN9 is ignored regardless of clock edge.
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