DS92LV1224_15 Datasheet, PDF (7/23 Pages) Texas Instruments – 30-66 MHz 10 Bit Bus LVDS Deserializer

DS92LV1224
www.ti.com
SNLS189A – APRIL 2005 – REVISED APRIL 2013
Electrical Characteristics^(1)(2)(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Units
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply to pins
ROUT, RCLK, LOCK = outputs)
V_IH
High Level Input Voltage
2.0
V_CC
V
V_IL
Low Level Input Voltage
GND
0.8
V
V_CL
Input Clamp Voltage
I_CL = −18 mA
−0.62 −1.5
V
I_IN
Input Current
V_IN = 0V or 3.6V
−10
±1
+15
μA
V_OH
High Level Output Voltage
I_OH = −9 mA
2.2
3.0
V_CC
V
V_OL
Low Level Output Voltage
I_OL = 9 mA
GND 0.25
0.5
V
I_OS
Output Short Circuit Current
VOUT = 0V
−15
−47
−85
mA
I_OZ
TRI-STATE Output Current
PWRDN or REN = 0.8V, V_OUT = 0V or VCC
−10
±0.1
+10
μA
DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−)
VTH
VTL
Differential Threshold High Voltage
Differential Threshold Low Voltage
VCM = +1.1V
+6
+50
mV
−50
−12
mV
I_IN
Input Current
V_IN = +2.4V, V_CC = 3.6V or 0V
V_IN = 0V, V_CC = 3.6V or 0V
DESERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC)
−10
±1
+15
μA
−10 ±0.05 +10
μA
Deserializer Supply Current Worst
I_CCR
Case
C_L = 15 pF
See Figure 2
f = 30 MHz
f = 40 MHz
f = 66 MHz
58
75
mA
58
75
mA
90
110
mA
I_CCXR
Deserializer Supply Current
Powerdown
PWRDN = 0.8V, REN = 0.8V
0.36
1.0
mA
(1) Typical values are given for V_CC = 3.3V and T_A = +25°C.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) For the purpose of specifying deserializer PLL performance, tDSR1 and tDSR2 are specified with the REFCLK running and stable, and
with specific conditions for the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either
t_DSR1 timing or t_DSR2 timing. t_DSR1 is the time required for the deserializer to indicate lock upon power-up or when leaving the power-
down mode. Synchronization patterns should be sent to the device before initiating either condition. t_DSR2 is the time required to indicate
lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change from not receiving data to receiving
synchronization patterns (SYNCPATs).
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_RFCP
t_RFDC
t_RFCP /
t_TCP
t_RFTT
REFCLK Period
REFCLK Duty Cycle
Ratio of REFCLK to TCLK
REFCLK Transition Time
15.15
T
30
50
95
1
3
Max
33.33
70
105
6
Units
ns
%
ns
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