DS92LV1224_15 Datasheet, PDF (12/23 Pages) Texas Instruments – 30-66 MHz 10 Bit Bus LVDS Deserializer

DS92LV1224
SNLS189A – APRIL 2005 – REVISED APRIL 2013
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SW - Setup and Hold Time (Internal Data Sampling Window)
t_DJIT - Serializer Output Bit Position Jitter that results from Jitter on TCLK
t_RNM = Receiver Noise Margin Time
Figure 10. Receiver Bus LVDS Input Skew Margin
Deserializer Truth Table^(4)(5)(6)
PWRDN
H
H
L
H
INPUTS
REN
H
H
X
L
ROUT [0:9]
Z
Active
Z
Z
OUTPUTS
LOCK
H
L
Z
Active
RCLK
Z
Active
Z
Z
(4) LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream.
(5) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined
by RCLK_R/F
(6) ROUT and RCLK are TRI-STATED when LOCK is asserted High.
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