DS92LV1224_15 Datasheet, PDF (14/23 Pages) Texas Instruments – 30-66 MHz 10 Bit Bus LVDS Deserializer

DS92LV1224
SNLS189A – APRIL 2005 – REVISED APRIL 2013
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HOT INSERTION
All the BLVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s)
makes contact first, then the VCC pin(s), and then the I/O pins. When removing, the I/O pins should be
unplugged first, then the VCC, then the Ground. Random lock hot insertion is illustrated in Figure 13
PCB CONSIDERATIONS
The Bus LVDS Serializer and Deserializer should be placed as close to the edge connector as possible. In
multiple Deserializer applications, the distance from the Deserializer to the slot connector appears as a stub to
the Serializer driving the backplane traces. Longer stubs lower the impedance of the bus, increase the load on
the Serializer, and lower the threshold margin at the Deserializers. Deserializer devices should be placed much
less than one inch from slot connectors. Because transition times are very fast on the Serializer Bus LVDS
outputs, reducing stub lengths as much as possible is the best method to ensure signal integrity.
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-to-point configuration of a backplane, through a PCB
trace, or through twisted pair cable. In point-to-point configuration, the transmission media need only be
terminated at the receiver end. Please note that in point-to-point configuration, the potential of offsetting the
ground levels of the Serializer vs. the Deserializer must be considered. Also, Bus LVDS provides a +/− 1.2V
common mode range at the receiver inputs.
Failsafe Biasing for the DS92LV1224
The DS92LV1224 has an improved input threshold sensitivity of +/− 50mV versus +/− 100mV for the
DS92LV1210 or DS92LV1212. This allows for greater differential noise margin in the DS92LV1224. However, in
cases where the receiver input is not being actively driven, the increased sensitivity of the DS92LV1224 can
pickup noise as a signal and cause unintentional locking . For example, this can occur when the input cable is
disconnected.
External resistors can be added to the receiver circuit board to prevent noise pick-up. Typically, the non-inverting
receiver input is pulled up and the inverting receiver input is pulled down by high value resistors. the pull-up and
pull-down resistors (R₁ and R₂) provide a current path through the termination resistor (R_L) which biases the
receiver inputs when they are not connected to an active driver. The value of the pull-up and pull-down resistors
should be chosen so that enough current is drawn to provide a +15mV drop across the termination resistor.
Please see Figure 11 for the Failsafe Biasing Setup.
USING T_DJIT AND T_RNM TO VALIDATE SIGNAL QUALITY
The parameters t_DJIT and t_RNM can be used to generate an eye pattern mask to validate signal quality in an actual
application or in simulation.
The parameter t_DJIT measures the transmitter's ability to place data bits in the ideal position to be sampled by the
receiver. The typical t_DJIT parameter of −80 ps indicates that the crossing point of the Tx data is 80 ps ahead of
the ideal crossing point. The t_DJIT(min) and t_DJIT(max) parameters specify the earliest and latest, respectively, time
that a crossing will occur relative to the ideal position.
The parameter t_RNM is calculated by first measuring how much of the ideal bit the receiver needs to ensure
correct sampling. After determining this amount, what remains of the ideal bit that is available for external
sources of noise is called t_RNM. It is the offset from t_{DJIT(min or max)} for the test mask within the eye opening.
The vertical limits of the mask are determined by the DS92LV1224 receiver input threshold of +/− 50 mV.
Please refer to the eye mask pattern of Figure 11 for a graphic representation of t_DJIT and t_RNM.
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