DS92LV1224_15 Datasheet, PDF (10/23 Pages) Texas Instruments – 30-66 MHz 10 Bit Bus LVDS Deserializer

DS92LV1224
SNLS189A – APRIL 2005 – REVISED APRIL 2013
Figure 5. Deserializer Delay
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Timing shown for RCLK_R/F = LOW
t_HIGH
Duty Cycle (t_RDC) = _{tHIGH + tLOW}
Figure 6. Deserializer Data Valid Out Times
Figure 7. Deserializer TRI-STATE Test Circuit and Timing
10
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