TMS320TCI6608_14 Datasheet, PDF (74/244 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320TCI6608
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS623E—March 2014
3.2 Peripheral Selection After Device Reset
Several of the peripherals on the TMS320TCI6608 are controlled by the Power Sleep Controller (PSC). By default,
the PCIe, SRIO, and HyperLink are held in reset and clock-gated. The memories in these modules are also in a
low-leakage sleep mode. Software is required to turn these memories on. The software enables the modules (turns
on clocks and de-asserts reset) before these modules can be used.
If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the
module.
All other modules come up enabled by default and there is no special software sequence to enable. For more detailed
information on the PSC usage, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 72.
3.3 Device State Control Registers
The TMS320TCI6608 device has a set of registers that are used to provide the status or configure certain parts of its
peripherals. These registers are shown in Table 3-2.
Table 3-2
Device State Control Registers (Part 1 of 4)
Address Start
0x02620000
0x02620008
0x02620018
0x0262001C
0x02620020
0x02620024
0x02620038
0x0262003C
0x02620040
0x02620044
0x02620048
0x0262004C
0x02620050
0x02620054
0x02620058
0x0262005C
0x02620060
0x026200E0
0x02620110
0x02620118
0x02620130
0x02620134
0x02620138
0x0262013C
0x02620140
0x02620144
0x02620148
Address End
0x02620007
0x02620017
0x0262001B
0x0262001F
0x02620023
0x02620037
0x0262003B
0x0262003F
0x02620043
0x02620047
0x0262004B
0x0262004F
0x02620053
0x02620057
0x0262005B
0x0262005F
0x026200DF
0x0262010F
0x02620117
0x0262012F
0x02620133
0x02620137
0x0262013B
0x0262013F
0x02620143
0x02620147
0x0262014B
Size
8B
16B
4B
4B
4B
20B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
128B
48B
8B
Field
Reserved
Reserved
JTAGID
Reserved
DEVSTAT
Reserved
KICK0
KICK1
DSP_BOOT_ADDR0
DSP_BOOT_ADDR1
DSP_BOOT_ADDR2
DSP_BOOT_ADDR3
DSP_BOOT_ADDR4
DSP_BOOT_ADDR5
DSP_BOOT_ADDR6
DSP_BOOT_ADDR7
Reserved
Reserved
MACID
24B Reserved
4B LRSTNMIPINSTAT_CLR
4B RESET_STAT_CLR
4B Reserved
4B BOOTCOMPLETE
4B Reserved
4B RESET_STAT
4B LRSTNMIPINSTAT
Description
See section 3.3.3
See section 3.3.1
See section 3.3.4
The boot address for C66x DSP CorePac0, see section 3.3.5
The boot address for C66x DSP CorePac1, see section 3.3.5
The boot address for C66x DSP CorePac2, see section 3.3.5
The boot address for C66x DSP CorePac3, see section 3.3.5
The boot address for C66x DSP CorePac4, see section 3.3.5
The boot address for C66x DSP CorePac5, see section 3.3.5
The boot address for C66x DSP CorePac6, see section 3.3.5
The boot address for C66x DSP CorePac7, see section 3.3.5
See section 7.22 ‘‘Gigabit Ethernet (GbE) Switch Subsystem’’ on
page 226
See section 3.3.7
See section 3.3.9
See section 3.3.10
See section 3.3.8
See section 3.3.6
74 Device Configuration
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