TMS320TCI6608_14 Datasheet, PDF (172/244 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320TCI6608
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS623E—March 2014
Table 7-38 CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 3 of 5)
Input Event# on CIC
73
74
75
76
77
78
79
80
81
81
82
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
105
107
108
109
110
111
112
113
System Interrupt
Description
TRACER_CORE_0_INTD
Tracer sliding time window interrupt for individual core
TRACER_CORE_1_INTD
Tracer sliding time window interrupt for individual core
TRACER_CORE_2_INTD
Tracer sliding time window interrupt for individual core
TRACER_CORE_3_INTD
Tracer sliding time window interrupt for individual core
TRACER_DDR_INTD
Tracer sliding time window interrupt for DDR3 EMIF1
TRACER_MSMC_0_INTD
Tracer sliding time window interrupt for MSMC SRAM bank0
TRACER_MSMC_1_INTD
Tracer sliding time window interrupt for MSMC SRAM bank1
TRACER_MSMC_2_INTD
Tracer sliding time window interrupt for MSMC SRAM bank2
TRACER_MSMC_3_INTD
Tracer sliding time window interrupt for MSMC SRAM bank3
TRACER_CFG_INTD
Tracer sliding time window interrupt for CFG0 TeraNet
TRACER_QM_CFG_INTD
Tracer sliding time window interrupt for QM_SS CFG
TRACER_QM_DMA_INTD
Tracer sliding time window interrupt for QM_SS slave
TRACER_SM_INTD
Tracer sliding time window interrupt for semaphore
PSC_ALLINT
Power/sleep controller interrupt
MSMC_SCRUB_CERROR
Correctable (1-bit) soft error detected during scrub cycle
BOOTCFG_INTD
Chip-level MMR error register
Reserved
MPU0_INTD (MPU0_ADDR_ERR_INT and MPU0 addressing violation interrupt and protection violation interrupt.
MPU0_PROT_ERR_INT combined)
QM_INT_PASS_TXQ_PEND_13
Queue manager pend event
MPU1_INTD (MPU1_ADDR_ERR_INT and MPU1 addressing violation interrupt and protection violation interrupt.
MPU1_PROT_ERR_INT combined)
QM_INT_PASS_TXQ_PEND_14
Queue manager pend event
MPU2_INTD (MPU2_ADDR_ERR_INT and MPU2 addressing violation interrupt and protection violation interrupt.
MPU2_PROT_ERR_INT combined)
QM_INT_PASS_TXQ_PEND_15
Queue manager pend event
MPU3_INTD (MPU3_ADDR_ERR_INT and MPU3 addressing violation interrupt and protection violation interrupt.
MPU3_PROT_ERR_INT combined)
QM_INT_PASS_TXQ_PEND_16
Queue manager pend event
MSMC_dedc_cerror
Correctable (1-bit) soft error detected on SRAM read
MSMC_dedc_nc_error
Non-correctable (2-bit) soft error detected on SRAM read
MSMC_scrub_nc_error
Non-correctable (2-bit) soft error detected during scrub cycle
Reserved
MSMC_mpf_error8
Memory protection fault indicators for each system master PrivID
MSMC_mpf_error9
Memory protection fault indicators for each system master PrivID
MSMC_mpf_error10
Memory protection fault indicators for each system master PrivID
MSMC_mpf_error11
Memory protection fault indicators for each system master PrivID
MSMC_mpf_error12
Memory protection fault indicators for each system master PrivID
MSMC_mpf_error13
Memory protection fault indicators for each system master PrivID
MSMC_mpf_error14
Memory protection fault indicators for each system master PrivID
MSMC_mpf_error15
Memory protection fault indicators for each system master PrivID
DDR3_ERR
DDR3 EMIF error interrupt
VUSR_INT_O
HyperLink interrupt
INTDST0
RapidIO interrupt
INTDST1
RapidIO interrupt
172 Peripheral Information and Electrical Specifications
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