TMS320TCI6608_14 Datasheet, PDF (192/244 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320TCI6608
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS623E—March 2014
7.11 Memory Protection Unit (MPU)
The TCI6608 supports four MPUs:
• One MPU is used to protect the main CORE/3 CFG TeraNet (the CFG space of all slave devices on the TeraNet
is protected by the MPU).
• Two MPUs are used for QM_SS (one for the DATA PORT port and one for the CFG PORT port).
• One MPU is used for Semaphore.
This section contains MPU register map and details of device-specific MPU registers only. For MPU features and
details of generic MPU registers, see the Memory Protection Unit (MPU) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 72.
The following tables show the configuration of each MPU and the memory regions protected by each MPU.
Table 7-49 MPU Default Configuration
Setting
Default permission
Number of allowed IDs supported
Number of programmable ranges supported
Compare width
End of Table 7-49
MPU0
(Main CFG TeraNet)
Assume allowed
16
16
1KB granularity
MPU1
(QM_SS DATA PORT)
Assume allowed
16
5
1KB granularity
MPU2
(QM_SS CFG PORT)
Assume allowed
16
16
1KB granularity
MPU3
(Semaphore)
Assume allowed
16
1
1KB granularity
Table 7-50
MPU0
MPU1
MPU2
MPU3
MPU Memory Regions
Memory Protection
Main CFG TeraNet
QM_SS DATA PORT
QM_SS CFG PORT
Semaphore
Start Address
0x01D00000
0x34000000
0x02A00000
0x02640000
End Address
0x026207FF
0x340BFFFF
0x02ABFFFF
0x026407FF
Table 7-51 shows the privilege ID of each CORE and every mastering peripheral. Table 7-51 also shows the privilege
level (supervisor vs. user), security level (secure vs. non-secure), and access type (instruction read vs. data/DMA read
or write) of each master on the device. In some cases, a particular setting depends on software being executed at the
time of the access or the configuration of the master peripheral.
Table 7-51 Privilege ID Settings (Part 1 of 2)
Privilege ID
0
1
2
3
4
5
6
7
8
Master
CorePac0
CorePac1
CorePac2
CorePac3
CorePac4
CorePac5
CorePac6
CorePac7
Network Coprocessor
Packet DMA
Privilege Level
SW dependant, driven by MSMC
SW dependant, driven by MSMC
SW dependant, driven by MSMC
SW dependant, driven by MSMC
SW dependant, driven by MSMC
SW dependant, driven by MSMC
SW dependant, driven by MSMC
SW dependant, driven by MSMC
User
Security Level
SW dependant
SW dependant
SW dependant
SW dependant
SW dependant
SW dependant
SW dependant
SW dependant
Non-secure
Access Type
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
192 Peripheral Information and Electrical Specifications
Copyright 2014 Texas Instruments Incorporated
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