TMS320TCI6608_14 Datasheet, PDF (189/244 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320TCI6608
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS623E—March 2014
Table 7-45 IPC Generation Registers (IPCGRx) (Part 2 of 2)
Address Start
0x02620244
0x02620248
0x0262024C
0x02620250
0x02620254
0x02620258
0x0262025C
0x02620260
0x0262027C
0x02620280
0x02620284
0x02620288
0x0262028C
0x02620290
0x02620294
0x02620298
0x0262029C
0x026202A0
0x026202BC
End of Table 7-45
Address End
0x02620247
0x0262024B
0x0262024F
0x02620253
0x02620257
0x0262025B
0x0262025F
0x0262027B
0x0262027F
0x02620283
0x02620287
0x0262028B
0x0262028F
0x02620293
0x02620297
0x0262029B
0x0262029F
0x026202BB
0x026202BF
Size
Register Name
4B
IPCGR1
4B
IPCGR2
4B
IPCGR3
4B
IPCGR4
4B
IPCGR5
4B
IPCGR6
4B
IPCGR7
28B
Reserved
4B
IPCGRH
4B
IPCAR0
4B
IPCAR1
4B
IPCAR2
4B
IPCAR3
4B
IPCAR4
4B
IPCAR5
4B
IPCAR6
4B
IPCAR7
28B
Reserved
4B
IPCARH
Description
IPC Generation Register for CorePac1
IPC Generation Register for CorePac2
IPC Generation Register for CorePac3
IPC Generation Register for CorePac4
IPC Generation Register for CorePac5
IPC Generation Register for CorePac6
IPC Generation Register for CorePac7
Reserved
IPC Generation Register for Host
IPC Acknowledgement Register for CorePac0
IPC Acknowledgement Register for CorePac1
IPC Acknowledgement Register for CorePac2
IPC Acknowledgement Register for CorePac3
IPC Acknowledgement Register for CorePac4
IPC Acknowledgement Register for CorePac5
IPC Acknowledgement Register for CorePac6
IPC Acknowledgement Register for CorePac7
Reserved
IPC Acknowledgement Register for Host
7.10.4 NMI and LRESET
Non-maskable interrupts (NMI) can be generated by chip-level registers and the LRESET can be generated by
software writing into LPSC registers. LRESET and NMI can also be asserted by device pins or watchdog timers. One
NMI pin and one LRESET pin are shared by all CorePacs on the device. The CORESEL[3:0] pins can be configured
to select between the CorePacs available as shown in Table 7-46.
Table 7-46 LRESET and NMI Decoding (Part 1 of 2)
CORESEL[3:0] Pin Input LRESET Pin Input NMI Pin Input LRESETNMIEN Pin Input Reset Mux Block Output
XXXX
X
X
1
No local reset or NMI assertion.
0000
0
X
0
Assert local reset to CorePac0
0001
0
X
0
Assert local reset to CorePac1
0010
0
X
0
Assert local reset to CorePac2
0011
0
X
0
Assert local reset to CorePac3
0100
0
X
0
Assert local reset to CorePac4
0101
0
X
0
Assert local reset to CorePac5
0110
0
X
0
Assert local reset to CorePac6
0111
0
X
0
Assert local reset to CorePac7
1xxx
0
X
0
Assert local reset to all CorePacs
0000
1
1
0
De-assert local reset & NMI to CorePac0
0001
1
1
0
De-assert local reset & NMI to CorePac1
0010
1
1
0
De-assert local reset & NMI to CorePac2
0011
1
1
0
De-assert local reset & NMI to CorePac3
Copyright 2014 Texas Instruments Incorporated
Submit Documentation Feedback
Peripheral Information and Electrical Specifications 189