TMS320TCI6608_14 Datasheet, PDF (196/244 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320TCI6608
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS623E—March 2014
Table 7-53 MPU0 Registers (Part 2 of 2)
Offset
Name
274h
PROG7_MPEAR
278h
PROG7_MPPA
280h
PROG8_MPSAR
284h
PROG8_MPEAR
288h
PROG8_MPPA
290h
PROG9_MPSAR
294h
PROG9_MPEAR
298h
PROG9_MPPA
2A0h
PROG10_MPSAR
2A4h
PROG10_MPEAR
2A8h
PROG10_MPPA
2B0h
PROG11_MPSAR
2B4h
PROG11_MPEAR
2B8h
PROG11_MPPA
2C0h
PROG12_MPSAR
2C4h
PROG12_MPEAR
2C8h
PROG12_MPPA
2D0h
PROG13_MPSAR
2D4h
PROG13_MPEAR
2Dh
PROG13_MPPA
2E0h
PROG14_MPSAR
2E4h
PROG14_MPEAR
2E8h
PROG14_MPPA
2F0h
PROG15_MPSAR
2F4h
PROG15_MPEAR
2F8h
PROG15_MPPA
300h
FLTADDRR
304h
FLTSTAT
308h
FLTCLR
End of Table 7-53
Description
Programmable range 7, end address
Programmable range 7, memory page protection attributes
Programmable range 8, start address
Programmable range 8, end address
Programmable range 8, memory page protection attributes
Programmable range 9, start address
Programmable range 9, end address
Programmable range 9, memory page protection attributes
Programmable range 10, start address
Programmable range 10, end address
Programmable range 10, memory page protection attributes
Programmable range 11, start address
Programmable range 11, end address
Programmable range 11, memory page protection attributes
Programmable range 12, start address
Programmable range 12, end address
Programmable range 12, memory page protection attributes
Programmable range 13, start address
Programmable range 13, end address
Programmable range 13, memory page protection attributes
Programmable range 14, start address
Programmable range 14, end address
Programmable range 14, memory page protection attributes
Programmable range 15, start address
Programmable range 15, end address
Programmable range 15, memory page protection attributes
Fault address
Fault status
Fault clear
Table 7-54
Offset
0h
4h
10h
14h
18h
1Ch
20h
200h
204h
208h
MPU1 Registers (Part 1 of 2)
Name
REVID
CONFIG
IRAWSTAT
IENSTAT
IENSET
IENCLR
EOI
PROG0_MPSAR
PROG0_MPEAR
PROG0_MPPA
Description
Revision ID
Configuration
Interrupt raw status/set
Interrupt enable status/clear
Interrupt enable
Interrupt enable clear
End of interrupt
Programmable range 0, start address
Programmable range 0, end address
Programmable range 0, memory page protection attributes
196 Peripheral Information and Electrical Specifications
Copyright 2014 Texas Instruments Incorporated
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