TMS320TCI6608_14 Datasheet, PDF (11/244 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

List of Tables
TMS320TCI6608
SPRS623E—November 2010—Revised March 2014
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 2-10
Table 2-11
Table 2-12
Table 2-13
Table 2-14
Table 2-15
Table 2-16
Table 2-17
Table 2-18
Table 2-19
Table 2-20
Table 2-21
Table 2-22
Table 2-23
Table 2-24
Table 2-25
Table 2-26
Table 2-27
Table 2-28
Table 2-29
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 3-9
Table 3-10
Table 3-11
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . 17
Bootloader section in L2 SRAM . . . . . . . . . . . . . . . . 23
Boot Mode Pins: Boot Device Values . . . . . . . . . . . 25
Extended Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . 25
No Boot / EMIF16 Configuration
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Serial Rapid I/O Configuration
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Ethernet (SGMII) Configuration
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PCI Device Configuration Field Descriptions. . . . 27
BAR Config / PCIe Window Sizes . . . . . . . . . . . . . . . 28
I²C Master Mode Device Configuration Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
I²C Passive Mode Device Configuration Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SPI Device Configuration Field Descriptions . . . . 29
HyperLink Boot Device Configuration Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Boot Parameter Table Common Parameters . . . . 31
EMIF16 Boot Mode Parameter Table . . . . . . . . . . . 31
SRIO Boot Mode Parameter Table . . . . . . . . . . . . . . 32
Ethernet Boot Mode Parameter Table . . . . . . . . . . 32
PCIe Boot Mode Parameter Table . . . . . . . . . . . . . . 34
I²C Boot Mode Parameter Table. . . . . . . . . . . . . . . . 34
SPI Boot Mode Parameter Table. . . . . . . . . . . . . . . . 35
HyperLink Boot Mode Parameter Table . . . . . . . . 36
DDR3 Boot Parameter Table . . . . . . . . . . . . . . . . . . . 37
C66x DSP System PLL Configuration . . . . . . . . . . . 38
I/O Functional Symbol Definitions . . . . . . . . . . . . . 44
Terminal Functions — Signals and Control
by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Terminal Functions — Power and Ground. . . . . . 57
Terminal Functions — By Signal Name . . . . . . . . . 58
Terminal Functions — By Ball Number . . . . . . . . . 63
TMS320TCI6608 Device Configuration Pins. . . . . 73
Device State Control Registers . . . . . . . . . . . . . . . . . 74
Device Status Register Field Descriptions. . . . . . . 78
Device Configuration Register (DEVCFG) Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
JTAG ID Register (JTAGID) Field Descriptions . . . 79
DSP BOOT Address Register (DSP_BOOT_ADDRn)
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
LRESETNMI PIN Status Clear Register
(LRSTNMIPINSTAT_CLR) Field Descriptions . . . . . 81
Reset Status Register (RESET_STAT) Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Reset Status Clear Register (RESET_STAT_CLR) Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Boot Complete Register (BOOTCOMPLETE) Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 3-12
Table 3-13
Table 3-14
Table 3-15
Table 3-16
Table 3-17
Table 3-18
Table 3-19
Table 3-20
Table 3-21
Table 3-22
Table 3-23
Table 4-1
Table 4-2
Table 4-3
Table 5-1
Table 5-2
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Table 7-6
Table 7-7
Table 7-8
Table 7-9
Table 7-10
Table 7-11
Table 7-12
Table 7-13
Table 7-14
Table 7-15
Power State Control Register (PWRSTATECTL)
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
NMI Generation Register (NMIGRx)
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
IPC Generation Registers (IPCGRx)
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
IPC Acknowledgement Registers (IPCARx)
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
IPC Generation Registers (IPCGRH)
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
IPC Acknowledgement Register (IPCARH)
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Timer Input Selection Field Description
(TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Timer Output Selection Register (TOUTPSEL)
Field Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Reset Mux Register (RSTMUXx)
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
DSP Suspension Control Register
(DSP_SUSP_CTL) Field Descriptions. . . . . . . . . . . . .95
Device Speed Register (DEVSPEED)
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Chip Miscellaneous Control Register
(CHIP_MISC_CTL) Field Descriptions . . . . . . . . . . . .96
Switch Fabric Connection Matrix Section 1. . . . .101
Switch Fabric Connection Matrix Section 2. . . . .104
Switch Fabric Connection Matrix Section 3. . . . .105
Available Memory Page Protection Schemes . . .113
CorePac Revision ID Register (MM_REVID)
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . .116
Recommended Operating Conditions . . . . . . . . .117
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .118
Power Supply to Peripheral I/O Mapping . . . . . .119
Power Supply Rails on the TMS320TCI6608 . . . .121
Core Before IO Power Sequencing . . . . . . . . . . . . .124
IO Before Core Power Sequencing . . . . . . . . . . . . .126
Clock Sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
SmartReflex 4-Pin VID Interface Switching
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Clock Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
PSC Register Memory Map . . . . . . . . . . . . . . . . . . . .131
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Reset Timing Requirements . . . . . . . . . . . . . . . . . . .138
Reset Switching Characteristics Over
Recommended Operating Conditions . . . . . . . . .138
Boot Configuration Timing Requirements. . . . . .139
Main PLL Stabilization, Lock, and Reset Times . .142
PLL Controller Registers (Including Reset
Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
PLL Secondary Control Register (SECCTL) Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Copyright 2014 Texas Instruments Incorporated
Submit Documentation Feedback
List of Tables 11