LM3S818 Datasheet, PDF (74/572 Pages) Bookham, Inc. – Microcontroller

The Cortex-M3 Processor
2.5.3
2.5.4
Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 72. Figure 2-6 on page 74 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
Figure 2-6. Vector Table
Exception number IRQ number Offset
Vector
45
29
IRQ29
0x00B4
.
.
.
.
.
.
.
.
.
0x004C
18
2
IRQ2
0x0048
17
1
IRQ1
0x0044
16
0
IRQ0
0x0040
15
-1
Systick
0x003C
14
-2
PendSV
0x0038
13
Reserved
12
Reserved for Debug
11
-5
SVCall
0x002C
10
9
Reserved
8
7
6
-10
Usage fault
0x0018
5
-11
Bus fault
0x0014
4
-12
Memory management fault
0x0010
3
-13
Hard fault
0x000C
2
-14
NMI
0x0008
1
Reset
0x0004
Initial SP value
0x0000
On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
74
July 14, 2014
Texas Instruments-Production Data