LM3S818 Datasheet, PDF (104/572 Pages) Bookham, Inc. – Microcontroller

Cortex-M3 Peripherals
Register 9: Interrupt 0-3 Priority (PRI0), offset 0x400
Register 10: Interrupt 4-7 Priority (PRI1), offset 0x404
Register 11: Interrupt 8-11 Priority (PRI2), offset 0x408
Register 12: Interrupt 12-15 Priority (PRI3), offset 0x40C
Register 13: Interrupt 16-19 Priority (PRI4), offset 0x410
Register 14: Interrupt 20-23 Priority (PRI5), offset 0x414
Register 15: Interrupt 24-27 Priority (PRI6), offset 0x418
Register 16: Interrupt 28-29 Priority (PRI7), offset 0x41C
Note: This register can only be accessed from privileged mode.
The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible.
Each register holds four priority fields that are assigned to interrupts as follows:
PRIn Register Bit Field
Bits 31:29
Bits 23:21
Bits 15:13
Bits 7:5
Interrupt
Interrupt [4n+3]
Interrupt [4n+2]
Interrupt [4n+1]
Interrupt [4n]
See Table 2-9 on page 73 for interrupt assignments.
Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP
field in the Application Interrupt and Reset Control (APINT) register (see page 112) indicates the
position of the binary point that splits the priority and subpriority fields.
These registers can only be accessed from privileged mode.
Interrupt 0-3 Priority (PRI0)
Base 0xE000.E000
Offset 0x400
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTD
reserved
INTC
reserved
Type R/W
R/W
R/W
RO
RO
RO
RO
RO
R/W
R/W
R/W
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTB
reserved
INTA
reserved
Type R/W
R/W
R/W
RO
RO
RO
RO
RO
R/W
R/W
R/W
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:29
Name
INTD
Type
R/W
Reset
0x0
Description
Interrupt Priority for Interrupt [4n+3]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+3], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
104
July 14, 2014
Texas Instruments-Production Data