LM3S818 Datasheet, PDF (513/572 Pages) Bookham, Inc. – Microcontroller

Stellaris^® LM3S818 Microcontroller
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (this is set through the QEIINTEN register).
Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in
question has not occurred.
QEI Raw Interrupt Status (QEIRIS)
QEI0 base: 0x4002.C000
Offset 0x024
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IntError
IntDir
IntTimer IntIndex
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
2
1
0
Name
reserved
IntError
IntDir
IntTimer
IntIndex
Type
RO
RO
RO
RO
RO
Reset
0x00
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Phase Error Detected
Indicates that a phase error was detected.
Direction Change Detected
Indicates that the direction has changed.
Velocity Timer Expired
Indicates that the velocity timer has expired.
Index Pulse Asserted
Indicates that the index pulse has occurred.
July 14, 2014
513
Texas Instruments-Production Data