LM3S818 Datasheet, PDF (16/572 Pages) Bookham, Inc. – Microcontroller

Table of Contents
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 288
GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 291
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 293
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 294
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 295
GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 297
GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 298
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 299
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 300
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 301
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 302
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 303
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 304
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 305
GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 306
Watchdog Timer ........................................................................................................................... 307
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 311
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 312
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 313
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 314
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 315
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 316
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 317
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 318
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 319
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 320
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 321
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 322
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 323
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 324
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 325
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 326
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 327
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 328
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 329
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 330
Analog-to-Digital Converter (ADC) ............................................................................................. 331
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 341
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 342
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 343
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 344
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 345
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 346
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 350
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 351
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 353
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 354
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 355
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July 14, 2014
Texas Instruments-Production Data