LM3S818 Datasheet, PDF (147/572 Pages) Bookham, Inc. – Microcontroller

Stellaris^® LM3S818 Microcontroller
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state, please
refer to IEEE Standard 1149.1.
Figure 4-2. Test Access Port State Machine
Test Logic Reset
1
0
Run Test Idle
1
0
Select DR Scan
1
0
Capture DR
1
0
Shift DR
1
0
Exit 1 DR
1
0
Pause DR
1
0
Exit 2 DR
0
1
Update DR
10
Select IR Scan
1
0
Capture IR
1
0
Shift IR
1
0
Exit 1 IR
1
0
Pause IR
1
0
Exit 2 IR
0
1
Update IR
10
4.3.3
4.3.4
Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 149.
Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
July 14, 2014
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Texas Instruments-Production Data