MSP430FR5994 Datasheet, PDF (72/166 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54 – MARCH 2016
www.ti.com
6.12 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430FR58xx,
MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide (SLAU367).
6.12.1 Digital I/O
Up to nine 8-bit I/O ports are implemented (see Table 6-52 through Table 6-56 for control and
configuration registers):
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all pins of
ports P1, P2, P3, P4, P5, P6, P7, and P8.
• Read and write access to port control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• All pins of ports P1, P2, P3, P4, P5, P6, P7, P8, and PJ support capacitive touch functionality.
• No cross-currents during start-up.
NOTE
Configuration of Digital I/Os After BOR Reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and their module functions disabled. To enable the I/O functionality after
a BOR reset, first configure the ports and then clear the LOCKLPM5 bit. For details, refer to
the Configuration After Reset section of the "Digital I/O" chapter in the MSP430FR58xx,
MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide (SLAU367).
6.12.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch-crystal oscillator XT1 (LF), an internal very-low-
power low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements
of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources.
See Table 6-49 for control and configuration registers.
The clock system module provides the following clock signals:
• Auxiliary clock (ACLK). ACLK can be sourced from a 32-kHz watch crystal (LFXT1), the internal VLO,
or a digital external low-frequency (<50 kHz) clock source.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced from a high-frequency
crystal (HFXT2), the internal DCO, a 32-kHz watch crystal (LFXT1), the internal VLO, or a digital
external clock source.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to MCLK.
6.12.3 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout circuit provides the
proper internal reset signal to the device during power on and power off. The SVS circuitry detects if the
supply voltage drops below a safe level and below a user-selectable level. SVS circuitry is available on the
primary and core supplies. See Table 6-44 for control and configuration registers.
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Detailed Description
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