MSP430FR5994 Datasheet, PDF (25/166 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54 – MARCH 2016
4.4 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.13.
4.5 Buffer Types
Table 4-3 describes the buffer types that are referenced in Table 4-1.
Table 4-3. Buffer Type
BUFFER TYPE NOMINAL
(STANDARD) VOLTAGE
HYSTERESIS
Analog ⁽²⁾
3.0 V
No
LVCMOS
3.0 V
Power
(DVCC) ⁽⁴⁾
3.0 V
Power
(AVCC) ⁽⁴⁾
3.0 V
Power (DVSS
and AVSS)⁽⁴⁾
0V
(1) N/A = not applicable
(2) This is a switch, not a buffer.
(3) Only for input pins
(4) This is supply input, not a buffer.
Yes ⁽³⁾
No
No
No
PU OR PD⁽¹⁾
N/A
Programmable
N/A
NOMINAL
PU OR PD
STRENGTH
(µA) ⁽¹⁾
N/A
See Digital I/Os
N/A
OUTPUT
DRIVE
STRENGTH
(mA) ⁽¹⁾
N/A
See Typical
Characteristics
– Outputs
N/A
COMMENTS
See analog modules in
Specifications for details
SVS enables hysteresis on
DVCC
N/A
N/A
N/A
N/A
N/A
N/A
4.6 Connection of Unused Pins
Table 4-4 lists the correct termination of all unused pins.
Table 4-4. Connection of Unused Pins⁽¹⁾
PIN
POTENTIAL
COMMENT
AVCC
AVSS
Px.0 to Px.7
RST/NMI
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
DV_CC
DV_SS
Open
DV_CC or V_CC
Open
Switched to port function, output direction (PxDIR.n = 1)
47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF⁽²⁾) pulldown
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used, these should
be switched to port function, output direction. When used as JTAG pins, these pins should remain
open.
TEST
Open
This pin always has an internal pulldown enabled.
(1) For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 pins.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG
mode with TI tools like FET interfaces or GANG programmers.
Copyright © 2016, Texas Instruments Incorporated
Terminal Configuration and Functions
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