MSP430FR5994 Datasheet, PDF (67/166 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54 – MARCH 2016
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if
enabled by the corresponding signature).
The signatures are at 0FF80h and extend to higher addresses. Signatures are evaluated during device
start-up. Table 6-5 lists the device-specific signature locations.
A JTAG password can be programmed starting at address 0FF88h and extending to higher addresses.
The password can extend into the interrupt vector locations using the interrupt vector addresses as
additional bits for the password. The length of the JTAG password depends on the JTAG signature.
Refer to the chapter "System Resets, Interrupts, and Operating Modes, System Control Module (SYS)" in
the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide (SLAU367)
for details.
INTERRUPT SOURCE
System Reset
Power up, brownout, supply
supervisor
External reset RST
Watchdog time-out (watchdog
mode)
WDT, FRCTL MPU, CS,
PMM password violation
FRAM uncorrectable bit error
detection
MPU segment violation
Software POR, BOR
System NMI
Vacant memory access
JTAG mailbox
FRAM access time error
FRAM write protection error
FRAM bit error detection
MPU segment violation
User NMI
External NMI
Oscillator fault
Comparator_E
TB0
TB0
Watchdog timer (interval timer
mode)
eUSCI_A0 receive or transmit
eUSCI_B0 receive or transmit
Table 6-4. Interrupt Sources, Flags, and Vectors
INTERRUPT FLAG
SYSTEM
INTERRUPT
SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
PMMPORIFG, PMMBORIFG
(SYSRSTIV)^{(1) (2)}
Reset
VMAIFG
JMBINIFG, JMBOUTIFG
ACCTEIFG, WPIFG
CBDIFG, UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
(SYSSNIV) ^{(1) (3)}
NMIIFG, OFIFG
(SYSUNIV)^{(1) (3)}
CEIFG, CEIIFG
(CEIV) ⁽¹⁾
TB0CCR0.CCIFG
TB0CCR1.CCIFG ... TB0CCR6.CCIFG,
TB0CTL.TBIFG
(TB0IV) ⁽¹⁾
WDTIFG
UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA0IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA0IV) ⁽¹⁾
UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I²C mode)
(UCB0IV) ⁽¹⁾
(Non)maskable
(Non)maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
WORD
ADDRESS
0FFFEh
0FFFCh
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
PRIORITY
Highest
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from peripheral space.
(3) (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.
Copyright © 2016, Texas Instruments Incorporated
Detailed Description
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