MSP430FR5994 Datasheet, PDF (63/166 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54 – MARCH 2016
6 Detailed Description
6.1 Overview
The TI MSP430FR59xx family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals. The architecture, combined with seven low-power modes, is optimized to
achieve extended battery life for example in portable measurement applications. The devices features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency.
The device is an MSP430FR59xx family device with Low-Energy Accelerator (LEA_SC), up to six 16-bit
timers, up to eight eUSCIs that support UART, SPI, and I²C, a comparator, a hardware multiplier, an AES
accelerator, a 6-channel DMA, an RTC module with alarm capabilities, up to 67 I/O pins, and a high-
performance 12-bit ADC.
6.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses. The peripherals can be
managed with all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
6.3 Low-Energy Accelerator for Signal Conditioning (LEA_SC)
The LEA_SC is a hardware engine designed for operations that involve vector-based arithmetic and signal
conditioning. Compared to using the CPU for these operations, the LEA_SC offers up to 19 times faster
performance and up to 20 times less energy consumption when performing vector-based digital signal
processing computations such as FIR or IIR filtering, correlation, and FFT calculations. LEA_SC requires
MCLK to be operational; therefore, LEA_SC is enabled in active mode or LPM0 (see Table 6-1). When
LEA_SC is used, LEA_SC data operations are performed on a shared 4KB of RAM out of the 8KB of total
RAM (see Table 6-41). This shared RAM can also be used by the regular application. The MSP CPU and
the LEA_SC can run simultaneously and independently unless they access the same system RAM.
Copyright © 2016, Texas Instruments Incorporated
Detailed Description
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Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962