MSP430FR5994 Datasheet, PDF (33/166 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54 – MARCH 2016
5.10 Thermal Resistance Characteristics
θ_JA
θ_JC(TOP)
θ_JB
Ψ_JB
Ψ_JT
θ_JC(BOTTOM)
θ_JA
θ_JC(TOP)
θ_JB
Ψ_JB
Ψ_JT
θ_JC(BOTTOM)
θ_JA
θ_JC(TOP)
θ_JB
Ψ_JB
Ψ_JT
θ_JC(BOTTOM)
θ_JA
θ_JC(TOP)
θ_JB
Ψ_JB
Ψ_JT
PARAMETER
Junction-to-ambient thermal resistance, still air⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance⁽⁵⁾
Junction-to-ambient thermal resistance, still air⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance⁽⁵⁾
Junction-to-ambient thermal resistance, still air⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance⁽⁵⁾
Junction-to-ambient thermal resistance, still air⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
PACKAGE
VQFN-48 (RGZ)
LQFP-64 (PM)
LQFP-80 (PN)
NFBGA-87 (ZVW)
VALUE ⁽¹⁾
30.6
17.2
7.2
7.2
0.2
1.2
55.3
16.8
26.8
0.8
26.5
N/A
49.5
14.7
24.1
0.7
23.8
N/A
46
30
20
N/A
N/A
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) N/A = not applicable
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2016, Texas Instruments Incorporated
Specifications
33
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