TLC320AC02C_15 Datasheet, PDF (70/86 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

Appendix A
Primary Control Bits
The function of the primary-word control bits D01 and D00 and the hardware terminals FC0 and FC1 are
shown below. Any combinational state of D01, D00, FC1, and FC0 not shown is ignored.
BITS
D01 D00
0
0
0
0
0
0
0
0
0
1
1
0
1
1
CONTROL FUNCTION OF CONTROL BITS
TERMINALS
FC1 FC0
0
0 On the next falling edge of FS, the AIC receives DAC data D15 – D02 to DIN and
transmits the ADC data D15 – D00 from DOUT.
0
1 On the next falling edge of FS, the AIC receives DAC data D15 – D02 to DIN and
transmits the ADC data D15 – D00 from DOUT.
The phase adjustment is determined by the state of FC1 and FC0 such that on the
next rising edge of the next internal FS, the next ADC/DAC sampling time occurs later
by the number of MCLK periods equal to the value contained in the A′ register. When
the A′ register value is negative, the internal falling edge of FS occurs earlier.
1
0 On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and
transmits the ADC data D15 – D00 from DOUT.
The phase adjustment is determined by the state of FC1 and FC0 such that on the
rising edge of the next internal FS, the next ADC/DAC sample time occurs earlier by
the number of MCLK periods determined by the value contained in the A′ register.
When the A′ register value is negative, the internal falling edge of FS occurs later.
1
1 On the next falling edge of the primary FS, the AIC receives DAC data D15 – D02 at
DIN and transmits the ADC data D15 – D00 from DOUT.
When FC0 and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
sampling time as measured from the falling edge of the primary FS.
0
0 On the next falling edge of FS, the AIC receives DAC data D15 – D02 to DIN and
transmits the ADC data D15 – D00 from DOUT.
The phase adjustment is determined by the state of D01 and D00 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A′ register. When the A′
register value is negative, the falling edge of FS occurs earlier.
0
0 On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and
transmits the ADC data D15 – D00 from DOUT.
The phase adjustment is determined by the state of D01 and D00. On the next rising
edge of FS, the next ADC/DAC sampling time occurs earlier by the number of MCLK
periods determined by the value contained in the A′ register. When the A′ register
value is negative, the internal falling edge of FS occurs later.
0
0 On the next falling edge of FS, the AIC receives DAC data D15 – D02 to DIN and
transmits the ADC data D15 – D00 from DOUT.
When D00 and D01 are both high, the AIC initiates a secondary FS to receive a
secondary control word at DIN. The secondary frame sync occurs at 1/2 the sampling
time as measured from the falling edge of the primary FS.
A–1