TLC320AC02C_15 Datasheet, PDF (21/86 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

2.8.2 Notes on TLC320AC01/02 AIC Master-Slave Operation
Master/slave operational detail is summarized in the following notes:
1. The slave devices can be programmed independently of the master as long as the clock divide
register numbers are not changed. The gain settings, for example, can be changed
independently.
2. The method that is used to program a slave independently is to request a secondary
communication of the master and all slaves and ripple the delayed frame sync to the desired slave
device to be programmed.
3. Secondary frame syncs must be requested for all devices in the system or none. This is required
so that the master generates secondary frames for the slaves and allows the slaves to know that
the second frame syncs they receive are secondary frame syncs. Each device in the system must
receive a secondary frame request in its corresponding primary frame sync period (11 in the last
2 LSBs).
4. Calculation of the sampling frequency in terms of the master clock and the shift clock and the
respective register ratios is (see equations 4–6):
+ + Sampling frequency
f_s
FCLK
B register value
+
f(MCLK)
2 (A register value) (B register value)
(4)
Therefore,
+ f(MCLK)
f_s
2
(A register value)
(B register value)
(5)
and in terms of the shift clock frequency, since
+ f(MCLK) 4 f(SCLK)
then
+ ^{f(SCLK) (A register value) (B register value)}
f_s
2
+ Number of SCLK periods
Sampling period
(6)
5. The minimum number of shift clocks between falling edges of any two frame syncs is 18 because
the frame sync delay register minimum number is 18.
When a secondary communication is requested by the host, the master secondary frame sync
begins at the middle of the sampling period (followed by the slave secondary frame syncs), so all
primary frame sync intervals (master and slave) must occur within one-half the sampling time.
2–7