TLC320AC02C_15 Datasheet, PDF (23/86 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

2.9 Operating Frequencies
2.9.1 Master and Stand-Alone Operating Frequencies
The sampling (conversion) frequency is derived from the master-clock (MCLK) input by equation 11:
+ + fs Sampling (conversion) frequency
MCLK
(A register value) (B register value)
2 ⁽¹¹⁾
The inverse is the time between the falling edges of two successive primary frame-synchronization signals.
The input and output data clock (SCLK) frequency is given in equation 12:
+ SCLK frequency
MCLK frequency
4
(12)
2.9.2 Slave and Codec Operating Frequencies
The slave operating frequencies are either the default values or programmed by the control data word from
the master and codec conversion and the data frequencies are determined by the externally applied SCLK
and FS signals.
2.10 Switched-Capacitor Filter Frequency (FCLK)
The filter clock (FCLK) is an internal clock signal that determines the filter band-pass frequency and is the
B counter clock. The frequency of the filter clock is derived by equation 13:
+ FCLK
MCLK
(A register value)
2
(13)
2.11 Filter Bandwidths
The low-pass (LP) filter – 3 dB corner is derived in equation 14:
+ + f (LP)
FCLK
40
MCLK
40 (A register value) 2
(14)
The high-pass (HP) filter – 3 dB corner is derived in equation 15:
+ + f (HP)
Sampling frequency
200
MCLK
200 2 (A register value) (B register value)
(15)
2.12 Master and Stand-Alone Modes
The difference between the master and stand-alone modes is that in the stand-alone mode there are no
slave devices. Functionally these two modes are the same. In both, the AIC internally generates the shift
clock and frame-sync signal for the serial communications. These signals and the filter clock (FCLK) are
derived from the input master clock.The master clock applied at the MCLK input determines the internal
device timing. The shift clock frequency is a divide-by-four of the master clock frequency and shifts both the
input and output data at DIN and DOUT, respectively, during the frame-sync interval (16 shift clocks long).
To begin the communication sequence, the device is reset (see Section 2.2.1), and the first frame sync
occurs approximately 648 master clocks after the reset condition disappears.
2.12.1 Register Programming
All register programming occurs during secondary communications, and data is latched and valid on the
sixteenth falling edge of SCLK. After a reset condition, eight primary and secondary communications cycles
are required to set up the eight programmable registers. Registers 1 through 8 are programmed in
secondary communications intervals 1 through 8, respectively. If the default value for a particular register
is desired, that register does not need to be addressed during the secondary communications. The no-op
command addresses the pseudo-register (register 0), and no register programming takes place during this
communications. The no-op command allows phase shifts of the sampling period without reprogramming
any register.
During the eight register programming cycles, DOUT is in the high-impedance state. DOUT is released on
the rising edge of the eighth primary internal frame-sync interval. In addition, each register can be read back
2–9