TLC320AC02C_15 Datasheet, PDF (49/86 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

2V
SCLK
FS† _{0.8 V}
tf(SCLK)
2V
td(CH-FL)
0.8 V
DOUT‡
D15
D14
D13
tr(SCLK)
td(CH-DOUT)
D12
D11
2V
td(CH-FH)
2V
D2
D1
D0
tsu(DIN)
DIN
D15
D14
D13
D12
D11
D2
D1
D0
th(DIN)
† _{The time between falling edges of two primary FS signals is the conversion period.}
‡ _{The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling}
edge of the shift clock.
Figure 4 – 2. AIC Stand-Alone and Master-Mode Timing
2V
SCLK
§
FS†
DOUT‡
D15
tf(SCLK)
2V
0.8 V
tr(SCLK)
td(CH-DOUT)
D14
D13
D12
D11
tc(SCLK)
2V
2V
D2
D1
D0
tsu(DIN)
DIN
D15
D14
D13
D12
D11
D2
D1
D0
th(DIN)
† _{The time between falling edges of two primary FS signals is the conversion period.}
‡ _{The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling}
edge of the shift clock.
§ _{The high-to-low transition of FS must must occur within ±1/4 of a shift-clock period around the 2-V level of the shift clock}
for the codec mode.
Figure 4 – 3. AIC Slave and Codec Emulation Mode
4–2