TLC320AC02C_15 Datasheet, PDF (29/86 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

2.15.6 Enable Analog Input Summing
By setting bits DS01 and DS00 to 11 in register 5, the normal analog input voltage is summed with the
auxiliary input voltage. The gain for the analog input amplifier is set by data bits DS03 and DS02 in register 4.
2.15.7 DAC Channel (sin x)/x Error Correction
The (sin x)/x compensation filter is designed for zero (sin x)/x error using a B-register value of 15. Since the
filter cannot be removed from the signal path, operation using another B-register value results in an error
in the reconstructed analog output. The error is given by equation 19. Any error compensation needed by
a given application can be performed in the software.
+ ^{ȧȡ ǒ Ǔ ȣ sin}
2p A B
fMCLK
f
ȧ _{DAC channel frequency response error 20 log10}
15
B
(19)
ȧȢ _{ǒ Ǔ} ȧȤ _sin
30p A
fMCLK
f
where:
f
f_MCLK
A
B
= the frequency of interest
= the TLC320AC02 master-clock frequency
= the A-register value
= the B-register value
and the arguments of the sin functions are in radians.
2.16 Serial Communications
2.16.1 Stand-Alone and Master-Mode Word Sequence and Information Content During
Primary and Secondary Communications
For the stand-alone and master modes, the sequence in Figure 2–2 shows the relationship between the
primary and secondary communications interval, the data content into DIN, and the data content from
DOUT.
The TLC320AC02 can provide a phase-shift command or the next secondary communications interval by
decoding 1) the programmed state of the FC1 and FC0 inputs and the D01 and D00 data bits in the primary
data word, or 2) the state of the FC1 and FC0 inputs and the DS15 and DS14 data bits in the secondary
data word (see Table 2 – 3). When DS13 (the R/W bit) is the default value of 0, all 16 bits from DOUT are
0 during secondary communication. However, when the R/W bit is set to 1 in the secondary communication
control word, the secondary transmission from DOUT still contains 0s in the eight MSBs. The lower order
8 bits contain the data of the register currently being addressed. This function provides register status
information for the host.
2–15