TLC320AC02C_15 Datasheet, PDF (22/86 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

The first secondary frame-sync falling edge, therefore, occurs at the following time (see
equation 7):
+ + Time to first secondary frame sync
B
register
2
value
(FCLK
periods)
+ A register value B register value (number of MCLK periods)
A register value ₄ B register value _{(number of SCLK periods)}
(7)
6. Number of frame sync intervals using equation 8.
All master and slave primary frame sync intervals must occur within the time of equation 7.
Since 18 shift clocks are required for each frame sync interval, then the number of frame sync
intervals from equation 8 is:
+ ń Number of frame sync intervals A register value B register value
4 18 (SCLKs frame sync interval)
+ A register value B register value
72
(8)
7. Number of devices, master and slave, in terms of f(MCLK) and f_s.
Substituting the value from equation 5 for the A × B register value product gives the total number
of devices, including the master and all slaves that can be used, for a given master clock and
sampling frequency. Therefore, using equation 9:
+ Number of devices
f(MCLK)
144 fs
(9)
8. Number of devices, master and slave, if slave devices are reprogrammed.
Equation 9 does not include reprogramming the slave devices after the frame sync delay occurs.
So if programming is required after shifting the slave frame syncs by the FSD register, then the
total number of devices is given by equation 10 is:
+ Number of devices
f(MCLK)
288 fs
(10)
9. Example of the maximum number of devices if the slave devices are reprogrammed assuming
the following values:
+ + f(MCLK) 10.368 MHz, f_s 8 kHz
then from equation 10,
+ + Maximum number of devices
10.368 MHz
288 (8 kHz)
4.5
therefore, one master and three slaves can be used.
2–8