TLC320AC02C_15 Datasheet, PDF (52/86 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

Delay Is m Shift Clocks†
Master
FS
Master FSD,
Slave Device 1 FS
Slave Device 1 FSD,
Slave Device 2 FS
Delay Is m Shift Clocks†
Delay Is m Shift Clocks†
Slave Device 2 FSD,
Slave Device 3 FS
Slave Device
(n – 1) FSD,
Slave Device n FS
† _{The delay time from any FS signals to the corresponding FSD signals is m shift clocks with the value of m being the}
numerical value of the data programmed into the FSD register. In the master mode with slaves, the same data word
programs the master and all slave devices; therefore, master to slave 1, slave 1 to slave 2, slave 2 to slave 3, etc., have
the same delay time.
Figure 4 – 10. Master-Slave Frame-Sync Timing After a Delay Has Been
Programmed Into the FSD Registers
t=0
Sampling
Period
t=1
Master AIC
FS
Only Primary
MP
Frame Sync
MP
1/2 Period
Master AIC
Only Primary
FS
and Secondary
MP
MS
Frame Sync
FSD
Value
MP
MS
Master and Slave _FS
AIC Primary
Frame Sync
MP SP
MP SP
t=2
MP
MP
MP SP
Master and Slave
AIC Primary and ^FS
Secondary
Frame Sync
MP SP MS SS
MP SP MS SS
MP SP MS SS
MP = Master Primary
MS = Master Secondary
SP = Slave Primary
SS = Slave Secondary
Figure 4 – 11. Master and Slave Frame-Sync Sequence with One Slave
4–5