TLC320AC02C_15 Datasheet, PDF (13/86 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

Processor
5.184 MHz
10.368 MHz
MCLK
A Register
(8 bits)
A Register + A′ Register
(8 bits)
2s Complement
Control
Divide by 4
SCLK
1.296 MHz
2.592 MHz
FCLK [low-pass filter and
(sin x)/x filter clock]
Normal
Single, A-Counter
Period
One-Shot
Phase Shift
B Register
(8 bits)
Program Divide
A Counter
(8 bits)
576 kHz
Divide by 2
288 kHz
B Counter
Conversion
Rate
Figure 1–1. Control Flow Diagram
Table 1–1. Operating Frequencies
FCLK
(kHz)
LOW-PASS FILTER
BANDWIDTH
(kHz)
B REGISTER CONTENTS
(Program No. of Filter Clocks)
(Decimal)
CONVERSION
RATE
(kHz)
HIGH-PASS
POLE FREQUENCY
(Hz)
144
3.6
20 (see Note 1)
18
15
10 (see Note 2)
7.2
36
8
40
9.6
48
14.4
72
288
7.2
20 (see Note 1)
14.4
72
18
16
80
15
19.2
96
10 (see Notes 2 and 3)
28.8
144
432
10.8
20 (see Note 1)
21.6
108
18
24
120
15 (see Note 3)
28.8
144
10 (see Notes 2 and 3)
43.2
216
NOTES:
1. The B register can be programmed for values greater than 20; however, since the sample rate is lower than
7.2 kHz and the internal filter remains at 3.6 kHz, an external antialiasing filter is required.
2. When the B register is programmed for a value less than 10, the ADC and the DAC conversions are not
completed before the next frame-sync signal and the results are in error.
3. The maximum sampling rate for the ADC channel is 43.2 kHz. The maximum rate for the DAC channel is
25 kHz.
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