LM3S308 Datasheet, PDF (70/537 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

The Cortex-M3 Processor
2.5.3
Table 2-8. Exception Types (continued)
Exception Type
PendSV
SysTick
Interrupts
Vector
Number
14
15
16 and above
Priority^a
programmable^c
programmable^c
programmable^d
a. 0 is the default priority for all the programmable priorities.
b. See “Vector Table” on page 71.
c. See SYSPRI1 on page 115.
d. See PRIn registers on page 101.
Vector Address or
Offset^b
Activation
0x0000.0038
Asynchronous
0x0000.003C
Asynchronous
0x0000.0040 and above Asynchronous
Table 2-9. Interrupts
Vector Number
0-15
16
17
18
19
20
21
22
23
24
25-29
30
31
32
33
34
35
36
37
38
39
40
41
42-43
44
45
Interrupt Number (Bit
in Interrupt Registers)
-
0
1
2
3
4
5
6
7
8
9-13
14
15
16
17
18
19
20
21
22
23
24
25
26-27
28
29
Vector Address or
Offset
0x0000.0000 -
0x0000.003C
0x0000.0040
0x0000.0044
0x0000.0048
0x0000.004C
0x0000.0050
0x0000.0054
0x0000.0058
0x0000.005C
0x0000.0060
-
0x0000.0078
0x0000.007C
0x0000.0080
0x0000.0084
0x0000.0088
0x0000.008C
0x0000.0090
0x0000.0094
0x0000.0098
0x0000.009C
0x0000.00A0
0x0000.00A4
-
0x0000.00B0
0x0000.00B4
Description
Processor exceptions
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
GPIO Port E
UART0
UART1
SSI0
I²C0
Reserved
ADC0 Sequence 0
ADC0 Sequence 1
ADC0 Sequence 2
ADC0 Sequence 3
Watchdog Timer 0
Timer 0A
Timer 0B
Timer 1A
Timer 1B
Timer 2A
Timer 2B
Analog Comparator 0
Reserved
System Control
Flash Memory Control
Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
70
June 18, 2012
Texas Instruments-Production Data