LM3S308 Datasheet, PDF (10/537 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Table of Contents
Figure 13-1. I²C Block Diagram ............................................................................................. 439
Figure 13-2. I²C Bus Configuration ........................................................................................ 440
Figure 13-3. START and STOP Conditions ............................................................................. 440
Figure 13-4. Complete Data Transfer with a 7-Bit Address ....................................................... 441
Figure 13-5. R/S Bit in First Byte ............................................................................................ 441
Figure 13-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 441
Figure 13-7. Master Single SEND .......................................................................................... 444
Figure 13-8. Master Single RECEIVE ..................................................................................... 445
Figure 13-9. Master Burst SEND ........................................................................................... 446
Figure 13-10. Master Burst RECEIVE ...................................................................................... 447
Figure 13-11. Master Burst RECEIVE after Burst SEND ............................................................ 448
Figure 13-12. Master Burst SEND after Burst RECEIVE ............................................................ 449
Figure 13-13. Slave Command Sequence ................................................................................ 450
Figure 14-1. Analog Comparator Module Block Diagram ......................................................... 474
Figure 14-2. Structure of Comparator Unit .............................................................................. 475
Figure 14-3. Comparator Internal Reference Structure ............................................................ 476
Figure 15-1. 48-Pin QFP Package Pin Diagram ...................................................................... 486
Figure 18-1. Load Conditions ................................................................................................ 498
Figure 18-2. JTAG Test Clock Input Timing ............................................................................. 499
Figure 18-3. JTAG Test Access Port (TAP) Timing .................................................................. 500
Figure 18-4. JTAG TRST Timing ............................................................................................ 500
Figure 18-5. External Reset Timing (RST) .............................................................................. 501
Figure 18-6. Power-On Reset Timing ..................................................................................... 501
Figure 18-7. Brown-Out Reset Timing .................................................................................... 501
Figure 18-8. Software Reset Timing ....................................................................................... 502
Figure 18-9. Watchdog Reset Timing ..................................................................................... 502
Figure 18-10. LDO Reset Timing ............................................................................................. 502
Figure 18-11. ADC Input Equivalency Diagram ......................................................................... 504
Figure 18-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 505
Figure 18-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 505
Figure 18-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 506
Figure 18-15. I²C Timing ......................................................................................................... 507
Figure D-1. Stellaris LM3S308 48-Pin LQFP Package ........................................................... 532
Figure D-2. 48-Pin LQFP Tray Dimensions ........................................................................... 534
Figure D-3. 48-Pin LQFP Tape and Reel Dimensions ............................................................. 536
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June 18, 2012
Texas Instruments-Production Data