LM3S308 Datasheet, PDF (212/537 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Internal Memory
3. Poll the FMC register until the ERASE bit is cleared.
6.3.2.3 To perform a mass erase of the flash
1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register.
2. Poll the FMC register until the MERASE bit is cleared.
6.4 Register Map
Table 6-2 on page 212 lists the Flash memory and control registers. The offset listed is a hexadecimal
increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC register
offsets are relative to the Flash memory control base address of 0x400F.D000. The Flash memory
protection register offsets are relative to the System Control base address of 0x400F.E000.
Table 6-2. Flash Register Map
Offset Name
Type
Reset
Description
Flash Memory Control Registers (Flash Control Offset)
0x000 FMA
R/W
0x0000.0000
0x004 FMD
R/W
0x0000.0000
0x008 FMC
R/W
0x0000.0000
0x00C FCRIS
RO
0x0000.0000
0x010 FCIM
R/W
0x0000.0000
0x014 FCMISC
R/W1C 0x0000.0000
Flash Memory Protection Registers (System Control Offset)
0x130 FMPRE
R/W
0x8000.00FF
0x134 FMPPE
R/W
0x0000.00FF
0x140 USECRL
R/W
0x18
Flash Memory Address
Flash Memory Data
Flash Memory Control
Flash Controller Raw Interrupt Status
Flash Controller Interrupt Mask
Flash Controller Masked Interrupt Status and Clear
Flash Memory Protection Read Enable
Flash Memory Protection Program Enable
USec Reload
See
page
213
214
215
217
218
219
222
223
221
6.5 Flash Register Descriptions (Flash Control Offset)
This section lists and describes the Flash Memory registers, in numerical order by address offset.
Registers in this section are relative to the Flash control base address of 0x400F.D000.
212
June 18, 2012
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