LM3S308 Datasheet, PDF (174/537 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

System Control
Register 10: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register is used to automatically switch from the main oscillator to the internal oscillator when
entering Deep-Sleep mode. The system clock source is the main oscillator by default. When this
register is set, the internal oscillator is powered up and the main oscillator is powered down. When
the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency
it had at the onset of Deep-Sleep mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IOSC
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:1
0
Name
reserved
IOSC
Type
RO
R/W
Reset
0x0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
IOSC Clock Source
When set, forces IOSC to be clock source during Deep-Sleep (overrides
DSOSCSRC field if set)
174
June 18, 2012
Texas Instruments-Production Data