LM3S308 Datasheet, PDF (61/537 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S308 Microcontroller
2.4.2
2.4.3
■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 62).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.
Behavior of Memory Accesses
Table 2-5 on page 61 shows the behavior of accesses to each region in the memory map. See
“Memory Regions, Types and Attributes” on page 60 for more information on memory types and
the XN attribute. Stellaris devices may have reserved memory areas within the address ranges
shown below (refer to Table 2-4 on page 59 for more information).
Table 2-5. Memory Access Behavior
Address Range
Memory Region
0x0000.0000 - 0x1FFF.FFFF Code
Memory Type Execute
Never
(XN)
Normal
-
0x2000.0000 - 0x3FFF.FFFF SRAM
Normal
-
0x4000.0000 - 0x5FFF.FFFF Peripheral
Device
XN
0x6000.0000 - 0x9FFF.FFFF External RAM
Normal
-
0xA000.0000 - 0xDFFF.FFFF External device Device
XN
0xE000.0000- 0xE00F.FFFF Private peripheral Strongly
XN
bus
Ordered
0xE010.0000- 0xFFFF.FFFF Reserved
-
-
Description
This executable region is for program code.
Data can also be stored here.
This executable region is for data. Code
can also be stored here. This region
includes bit band and bit band alias areas
(see Table 2-6 on page 63).
This region includes bit band and bit band
alias areas (see Table 2-7 on page 63).
This executable region is for data.
This region is for external device memory.
This region includes the NVIC, system
timer, and system control block.
-
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M3 has separate buses that can perform
instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see “Memory Protection Unit (MPU)” on page 85.
June 18, 2012
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