LM3S308 Datasheet, PDF (118/537 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Cortex-M3 Peripherals
Register 27: System Handler Control and State (SYSHNDCTRL), offset 0xD24
Note: This register can only be accessed from privileged mode.
The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the
usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status
of the system handlers.
If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as
a hard fault.
This register can be modified to change the pending or active status of system exceptions. An OS
kernel can write to the active bits to perform a context switch that changes the current exception
type.
Caution – Software that changes the value of an active bit in this register without correct adjustment
to the stacked content can cause the processor to generate a fault exception. Ensure software that writes
to this register retains and subsequently restores the current active status.
If the value of a bit in this register must be modified after enabling the system handlers, a
read-modify-write procedure must be used to ensure that only the required bit is modified.
System Handler Control and State (SYSHNDCTRL)
Base 0xE000.E000
Offset 0xD24
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
Type
Reset
15
SVC
R/W
0
14
BUSP
R/W
0
13
12
11
MEMP USAGEP TICK
R/W
R/W
R/W
0
0
0
10
9
PNDSV reserved
R/W
RO
0
0
8
MON
R/W
0
23
RO
0
7
SVCA
R/W
0
22
21
20
RO
RO
RO
0
0
0
6
5
4
reserved
RO
RO
RO
0
0
0
19
18
17
USAGE BUS
RO
R/W
R/W
0
0
0
16
MEM
R/W
0
3
USGA
R/W
0
2
reserved
RO
0
1
BUSA
R/W
0
0
MEMA
R/W
0
Bit/Field
31:19
18
Name
reserved
USAGE
Type
RO
R/W
Reset
0x000
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Usage Fault Enable
Value Description
0 Disables the usage fault exception.
1 Enables the usage fault exception.
17
BUS
R/W
0
Bus Fault Enable
Value Description
0 Disables the bus fault exception.
1 Enables the bus fault exception.
118
June 18, 2012
Texas Instruments-Production Data