LM3S5D91-IQC80-A1 Datasheet, PDF (7/1342 Pages) Texas Instruments – Stellaris LM3S5D91 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5D91 Microcontroller
13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 684
13.1 Block Diagram ............................................................................................................ 685
13.2 Signal Description ....................................................................................................... 685
13.3 Functional Description ................................................................................................. 687
13.3.1 Transmit/Receive Logic ............................................................................................... 688
13.3.2 Baud-Rate Generation ................................................................................................. 688
13.3.3 Data Transmission ...................................................................................................... 689
13.3.4 Serial IR (SIR) ............................................................................................................. 689
13.3.5 ISO 7816 Support ....................................................................................................... 690
13.3.6 Modem Handshake Support ......................................................................................... 691
13.3.7 LIN Support ................................................................................................................ 692
13.3.8 FIFO Operation ........................................................................................................... 693
13.3.9 Interrupts .................................................................................................................... 694
13.3.10 Loopback Operation .................................................................................................... 695
13.3.11 DMA Operation ........................................................................................................... 695
13.4 Initialization and Configuration ..................................................................................... 695
13.5 Register Map .............................................................................................................. 696
13.6 Register Descriptions .................................................................................................. 698
14 Synchronous Serial Interface (SSI) .................................................................... 748
14.1 Block Diagram ............................................................................................................ 749
14.2 Signal Description ....................................................................................................... 749
14.3 Functional Description ................................................................................................. 750
14.3.1 Bit Rate Generation ..................................................................................................... 751
14.3.2 FIFO Operation ........................................................................................................... 751
14.3.3 Interrupts .................................................................................................................... 751
14.3.4 Frame Formats ........................................................................................................... 752
14.3.5 DMA Operation ........................................................................................................... 759
14.4 Initialization and Configuration ..................................................................................... 760
14.5 Register Map .............................................................................................................. 761
14.6 Register Descriptions .................................................................................................. 762
15 Inter-Integrated Circuit (I²C) Interface ................................................................ 790
15.1 Block Diagram ............................................................................................................ 791
15.2 Signal Description ....................................................................................................... 791
15.3 Functional Description ................................................................................................. 792
15.3.1 I²C Bus Functional Overview ........................................................................................ 792
15.3.2 Available Speed Modes ............................................................................................... 794
15.3.3 Interrupts .................................................................................................................... 795
15.3.4 Loopback Operation .................................................................................................... 796
15.3.5 Command Sequence Flow Charts ................................................................................ 797
15.4 Initialization and Configuration ..................................................................................... 804
15.5 Register Map .............................................................................................................. 805
15.6 Register Descriptions (I²C Master) ............................................................................... 806
15.7 Register Descriptions (I²C Slave) ................................................................................. 819
16 Inter-Integrated Circuit Sound (I²S) Interface .................................................... 828
16.1 Block Diagram ............................................................................................................ 829
16.2 Signal Description ....................................................................................................... 829
16.3 Functional Description ................................................................................................. 831
October 05, 2012
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