LM3S5D91-IQC80-A1 Datasheet, PDF (486/1342 Pages) Texas Instruments – Stellaris LM3S5D91 Microcontroller

NRND: Not recommended for new designs.
External Peripheral Interface (EPI)
Figure 9-23. EPI Clock Operation, CLKGATE=1, WR2CYC=0
Clock
(EPI0S31)
WR
(EPI0S28)
Address
Data
Figure 9-24. EPI Clock Operation, CLKGATE=1, WR2CYC=1
Clock
(EPI0S31)
WR
(EPI0S28)
Address
Data
9.5 Register Map
Table 9-8 on page 486 lists the EPI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the base address of 0x400D.0000. Note that the EPI controller clock
must be enabled before the registers can be programmed (see page 268). There must be a delay
of 3 system clocks after the EPI module clock is enabled before any EPI module registers are
accessed.
Note:
A back-to-back write followed by a read of the same register reads the value that written
by the first write access, not the value from the second write access. (This situation only
occurs when the processor core attempts this action, the μDMA does not do this.). To read
back what was just written, another instruction must be generated between the write and
read. Read-write does not have this issue, so use of read-write for clear of error interrupt
cause is not affected.
Table 9-8. External Peripheral Interface (EPI) Register Map
Offset Name
Type
Reset
Description
0x000
0x004
0x010
0x010
0x010
0x010
0x014
EPICFG
EPIBAUD
EPISDRAMCFG
EPIHB8CFG
EPIHB16CFG
EPIGPCFG
EPIHB8CFG2
R/W
0x0000.0000 EPI Configuration
R/W
0x0000.0000 EPI Main Baud Rate
R/W
0x82EE.0000 EPI SDRAM Configuration
R/W
0x0000.FF00 EPI Host-Bus 8 Configuration
R/W
0x0000.FF00 EPI Host-Bus 16 Configuration
R/W
0x0000.0000 EPI General-Purpose Configuration
R/W
0x0000.0000 EPI Host-Bus 8 Configuration 2
See
page
488
489
491
493
496
500
505
486
October 05, 2012
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