LM3S5D91-IQC80-A1 Datasheet, PDF (522/1342 Pages) Texas Instruments – Stellaris LM3S5D91 Microcontroller

NRND: Not recommended for new designs.
External Peripheral Interface (EPI)
Register 27: EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200
This register allows selection of the FIFO levels which trigger an interrupt to the interrupt controller
or, more efficiently, a DMA request to the μDMA. The NBRFIFO select triggers on fullness such
that it triggers on match or above (more full). The WFIFO triggers on emptiness such that it triggers
on match or below (less entries).
It should be noted that the FIFO triggers are not identical to other such FIFOs in Stellaris peripherals.
In particular, empty and full triggers are provided to avoid wait states when using blocking operations.
The settings in this register are only meaningful if the μDMA is active or the interrupt is enabled.
Additionally, this register allows protection against writes stalling and notification of performing
blocking reads which stall for extra time due to preceding writes. The two functions behave in a
non-orthogonal way because read and write are not orthogonal.
The write error bit configures the system such that an attempted write to an already full WFIFO
abandons the write and signals an error interrupt to prevent accidental latencies due to stalling
writes.
The read error bit configures the system such that after a read has been stalled due to any preceding
writes in the WFIFO, the error interrupt is generated. Note that the excess stall is not prevented,
but an interrupt is generated after the fact to notify that it has happened.
EPI FIFO Level Selects (EPIFIFOLVL)
Base 0x400D.0000
Offset 0x200
Type R/W, reset 0x0000.0033
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
WFERR RSERR
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WRFIFO
reserved
RDFIFO
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
Bit/Field
31:18
17
Name
reserved
WFERR
Type
RO
R/W
Reset
0x0000
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write Full Error
Value Description
0 The Write Full error interrupt is disabled. Writes are stalled when
the WFIFO is full until a space becomes available but an error
is not generated. Note that the Cortex-M3 write buffer may hide
that stall if no other memory transactions are attempted during
that time.
1 This bit enables the Write Full error interrupt (WTFULL in the
EPIEISC register) to be generated when a write is attempted
and the WFIFO is full. The write stalls until a WFIFO entry
becomes available.
522
October 05, 2012
Texas Instruments-Production Data