LM3S5D91-IQC80-A1 Datasheet, PDF (187/1342 Pages) Texas Instruments – Stellaris LM3S5D91 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5D91 Microcontroller
4.5.2.4
4.5.2.5
4.5.2.6
GPIO pin has three associated digital signals that are included in the chain. These signals are input,
output, and output enable, and are arranged in that order as shown in the figure.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. The EXTEST instruction forces data out of the controller,
and the INTEST instruction forces data into the controller.
Figure 4-5. Boundary Scan Register Format
TDI I
N
O
U
T
O _... I
E
N
O
U
T
O
E
I
N
O
U
T
O _...
E
I
N
O
U
T
O TDO
E
1^st GPIO
m^th GPIO
(m+1)^th GPIO
GPIO n^th
APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
October 05, 2012
187
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