LM3S5D91-IQC80-A1 Datasheet, PDF (564/1342 Pages) Texas Instruments – Stellaris LM3S5D91 Microcontroller

General-Purpose Timers
NRND: Not recommended for new designs.
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Timer 0 base: 0x4003.0000
Timer 1 base: 0x4003.1000
Timer 2 base: 0x4003.2000
Timer 3 base: 0x4003.3000
Offset 0x024
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
7
6
5
4
3
2
1
0
TBMCINT CBECINT CBMCINT TBTOCINT
reserved
TAMCINT RTCCINT CAECINT CAMCINT TATOCINT
RO
W1C
W1C
W1C
W1C
RO
RO
RO
W1C
W1C
W1C
W1C
W1C
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:12
11
10
9
8
7:5
4
3
2
Name
reserved
TBMCINT
CBECINT
CBMCINT
TBTOCINT
reserved
TAMCINT
RTCCINT
CAECINT
Type
RO
W1C
W1C
W1C
W1C
RO
W1C
W1C
W1C
Reset Description
0x0000.0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
GPTM Timer B Match Interrupt Clear
Writing a 1 to this bit clears the TBMRIS bit in the GPTMRIS register
and the TBMMIS bit in the GPTMMIS register.
0
GPTM Timer B Capture Mode Event Interrupt Clear
Writing a 1 to this bit clears the CBERIS bit in the GPTMRIS register
and the CBEMIS bit in the GPTMMIS register.
0
GPTM Timer B Capture Mode Match Interrupt Clear
Writing a 1 to this bit clears the CBMRIS bit in the GPTMRIS register
and the CBMMIS bit in the GPTMMIS register.
0
GPTM Timer B Time-Out Interrupt Clear
Writing a 1 to this bit clears the TBTORIS bit in the GPTMRIS register
and the TBTOMIS bit in the GPTMMIS register.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
GPTM Timer A Match Interrupt Clear
Writing a 1 to this bit clears the TAMRIS bit in the GPTMRIS register
and the TAMMIS bit in the GPTMMIS register.
0
GPTM RTC Interrupt Clear
Writing a 1 to this bit clears the RTCRIS bit in the GPTMRIS register
and the RTCMIS bit in the GPTMMIS register.
0
GPTM Timer A Capture Mode Event Interrupt Clear
Writing a 1 to this bit clears the CAERIS bit in the GPTMRIS register
and the CAEMIS bit in the GPTMMIS register.
564
October 05, 2012
Texas Instruments-Production Data