LM3S5D91-IQC80-A1 Datasheet, PDF (54/1342 Pages) Texas Instruments – Stellaris LM3S5D91 Microcontroller

Architectural Overview
NRND: Not recommended for new designs.
1.3.4.4
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
■ Support for communication with ISO 7816 smart cards
■ Full modem handshake support (on UART1)
■ LIN protocol support
■ Standard FIFO-level and End-of-Transmission interrupts
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
I²C (see page 790)
The Inter-Integrated Circuit (I²C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL). The I²C bus interfaces to external I²C devices
such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on.
The I²C bus may also be used for system testing and diagnostic purposes in product development
and manufacture.
Each device on the I²C bus can be designated as either a master or a slave. Each I²C module
supports both sending and receiving data as either a master or a slave and can operate
simultaneously as both a master and a slave. Both the I²C master and slave can generate interrupts.
The LM3S5D91 microcontroller includes two I²C modules with the following features:
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October 05, 2012
Texas Instruments-Production Data